Add seven-segments module and integrate it into the top level

soc/top/top.vhd

@@ -14,7 +14,7 @@ use work.lt16soc_peripherals.all;
 
 entity lt16soc_top is
 generic(
-	programfilename : string := "../../programs/blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
+	programfilename : string := "../../programs/timer_blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
 );
 port(
 	-- clock signal
@@ -25,7 +25,10 @@ port(
 	led		: out std_logic_vector(7 downto 0);
 	
 	btn : in std_logic_vector(4 downto 0);
-	sw : in std_logic_vector(15 downto 0)
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0)
 );
 end entity lt16soc_top;
 
@@ -37,7 +40,7 @@ architecture RTL of lt16soc_top is
 
 	signal rst_gen	: std_logic;
 
-	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_1000_0000_0001";
+	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_1100_0000_0001";
 	constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
 
 	signal slvo	: wb_slv_out_vector := (others=> wbs_out_none);
@@ -200,5 +203,20 @@ begin
 	port map(
 		clk,rst_gen,slvi(CFG_TIMER),slvo(CFG_TIMER), irq_lines(3)
 	);
+	
+    segmentdev : wb_segment
+		generic map(
+			memaddr		=> CFG_BADR_SEG,
+			addrmask	=> CFG_MADR_SEG
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst,
+			wslvi	=> slvi(CFG_SEG),
+			wslvo	=> slvo(CFG_SEG),
+
+            anodes => anodes,
+            cathodes => cathodes
+		);
 
 end architecture RTL;