From 94f916d624d235dff5e11972c8ba9bc1303c465f Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Sun, 20 Nov 2022 15:47:57 +0100 Subject: [PATCH] Implement scrolling segment --- soc/lib/config.vhd | 4 +- soc/peripheral/peripherals.vhd | 42 ++-- soc/peripheral/scrolling_controller.vhd | 78 +++++--- soc/peripheral/scrolling_top.vhd | 242 +++++++++++++++++++++++ soc/peripheral/seven_segment_display.vhd | 89 ++++----- soc/testbench/scrolling_top_tb.vhd | 136 +++++++++++++ soc/testbench/segment_tb.vhd | 112 ++++++++--- 7 files changed, 566 insertions(+), 137 deletions(-) create mode 100644 soc/peripheral/scrolling_top.vhd create mode 100644 soc/testbench/scrolling_top_tb.vhd diff --git a/soc/lib/config.vhd b/soc/lib/config.vhd index 5ee83df..aae1339 100644 --- a/soc/lib/config.vhd +++ b/soc/lib/config.vhd @@ -41,7 +41,7 @@ package config is constant CFG_BADR_LED : generic_addr_type := 16#000F0000#; constant CFG_BADR_SW : generic_addr_type := 16#000F0004#; constant CFG_BADR_TIMER : generic_addr_type := 16#000F0008#; - constant CFG_BADR_SEG : generic_addr_type := 16#000F00A0#; + constant CFG_BADR_SCR : generic_addr_type := 16#000F00A0#; -- mask addr constant CFG_MADR_ZERO : generic_mask_type := 0; @@ -51,7 +51,7 @@ package config is constant CFG_MADR_LED : generic_mask_type := 16#3FFFFF#; -- size=1 byte constant CFG_MADR_SW : generic_mask_type := 16#3FFFFF# - (4 - 1); -- size=4 byte constant CFG_MADR_TIMER : generic_mask_type := 16#3FFFFF# - (8 - 1); -- size=8 byte (2 words) - constant CFG_MADR_SEG : generic_mask_type := 16#3FFFFF# - (4 - 1); -- size=4 byte + constant CFG_MADR_SCR : generic_mask_type := 16#3FFFFF# - (8 - 1); -- size=8 byte end package config; diff --git a/soc/peripheral/peripherals.vhd b/soc/peripheral/peripherals.vhd index 390f41b..f8dd4cb 100644 --- a/soc/peripheral/peripherals.vhd +++ b/soc/peripheral/peripherals.vhd @@ -57,37 +57,21 @@ package lt16soc_peripherals is ); end component; - component wb_segment is - generic( - memaddr : generic_addr_type; --:= CFG_BADR_SEG; - addrmask : generic_mask_type --:= CFG_BADR_SEG; - ); - port( - clk : in std_logic; - rst : in std_logic; - wslvi : in wb_slv_in_type; - wslvo : out wb_slv_out_type; - + component wb_scrolling is + generic( + memaddr : generic_addr_type; --:= CFG_BADR_SCR; + addrmask : generic_mask_type --:= CFG_MADR_SCR; + ); + port( + clk : in std_logic; + rst : in std_logic; + wslvi : in wb_slv_in_type; + wslvo : out wb_slv_out_type; + anodes : out std_logic_vector(7 downto 0); cathodes : out std_logic_vector(7 downto 0) - ); - end component; - - component wb_segment_adv is - generic( - memaddr : generic_addr_type; --:= CFG_BADR_SEG; - addrmask : generic_mask_type --:= CFG_BADR_SEG; - ); - port( - clk : in std_logic; - rst : in std_logic; - wslvi : in wb_slv_in_type; - wslvo : out wb_slv_out_type; - - anodes : out std_logic_vector(7 downto 0); - cathodes : out std_logic_vector(7 downto 0) - ); - end component; + ); + end component; end lt16soc_peripherals; diff --git a/soc/peripheral/scrolling_controller.vhd b/soc/peripheral/scrolling_controller.vhd index 66535e7..81b8011 100644 --- a/soc/peripheral/scrolling_controller.vhd +++ b/soc/peripheral/scrolling_controller.vhd @@ -23,6 +23,11 @@ architecture Behavioral of scrolling_controller is type state_type is (s_off, s_wait, s_update); signal state : state_type; + + signal sig_seg_data_in : std_logic; + signal sig_seg_shift : std_logic; + signal sig_seg_write : std_logic; + signal sig_seg_clear : std_logic; begin @@ -31,68 +36,67 @@ begin if clk'event and clk='1' then if rst = '1' then state <= s_off; - seg_clear <= '1'; cnt_start <= '0'; next_char <= '0'; - seg_data <= (others => '0'); - seg_off <= '0'; - seg_shift <= '0'; - seg_write <= '0'; + sig_seg_data_in <= '0'; + sig_seg_shift <= '0'; + sig_seg_write <= '0'; + sig_seg_clear <= '0'; else + sig_seg_data_in <= '0'; + case state is when s_off => if on_off = '0' then state <= s_off; - seg_shift <= '0'; - seg_write <= '0'; - seg_clear <= '0'; + sig_seg_shift <= '0'; + sig_seg_write <= '0'; + sig_seg_clear <= '0'; cnt_start <= '0'; next_char <= '0'; else state <= s_update; - seg_data <= hex_char(3 downto 0); - seg_shift <= '1'; - seg_write <= '1'; - seg_clear <= '0'; - seg_off <= hex_char(4); + sig_seg_data_in <= '1'; + sig_seg_shift <= '1'; + sig_seg_write <= '1'; + sig_seg_clear <= '0'; cnt_start <= '1'; next_char <= '1'; end if; when s_wait => if on_off = '1' then state <= s_off; - seg_clear <= '1'; + sig_seg_clear <= '1'; cnt_start <= '0'; next_char <= '0'; elsif cnt_done = '0' then state <= s_wait; - seg_shift <= '0'; - seg_write <= '0'; - seg_clear <= '0'; + sig_seg_shift <= '0'; + sig_seg_write <= '0'; + sig_seg_clear <= '0'; cnt_start <= '0'; next_char <= '0'; else -- cnt_cone = '1' state <= s_update; - seg_shift <= '0'; - seg_write <= '0'; - seg_clear <= '0'; + sig_seg_shift <= '0'; + sig_seg_write <= '0'; + sig_seg_clear <= '0'; cnt_start <= '1'; next_char <= '1'; end if; when s_update => if on_off = '0' then state <= s_wait; - seg_data <= hex_char(3 downto 0); - seg_shift <= '1'; - seg_write <= '1'; - seg_clear <= '0'; - seg_off <= hex_char(4); + sig_seg_data_in <= '1'; + sig_seg_shift <= '1'; + sig_seg_write <= '1'; + sig_seg_clear <= '0'; cnt_start <= '0'; next_char <= '0'; else state <= s_off; - seg_clear <= '1'; + sig_seg_clear <= '1'; cnt_start <= '0'; next_char <= '0'; end if; @@ -100,5 +104,27 @@ begin end if; end if; end process; + + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + seg_data <= (others => '0'); + seg_off <= '0'; + seg_shift <= '0'; + seg_write <= '0'; + seg_clear <= '1'; + else + if sig_seg_data_in = '1' then + seg_data <= hex_char(3 downto 0); + seg_off <= hex_char(4); + end if; + + seg_shift <= sig_seg_shift; + seg_write <= sig_seg_write; + seg_clear <= sig_seg_clear; + end if; + end if; + end process; end Behavioral; diff --git a/soc/peripheral/scrolling_top.vhd b/soc/peripheral/scrolling_top.vhd new file mode 100644 index 0000000..38befbb --- /dev/null +++ b/soc/peripheral/scrolling_top.vhd @@ -0,0 +1,242 @@ +-- See the file "LICENSE" for the full license governing this code. -- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.lt16x32_global.all; +use work.wishbone.all; +use work.config.all; + +entity wb_scrolling is + generic( + memaddr : generic_addr_type; --:= CFG_BADR_SCR; + addrmask : generic_mask_type --:= CFG_MADR_SCR; + ); + port( + clk : in std_logic; + rst : in std_logic; + wslvi : in wb_slv_in_type; + wslvo : out wb_slv_out_type; + + anodes : out std_logic_vector(7 downto 0); + cathodes : out std_logic_vector(7 downto 0) + ); +end wb_scrolling; + +architecture Behavioral of wb_scrolling is + + signal cnt_start : std_logic; + signal cnt_done : std_logic; + signal cnt_value : std_logic_vector(31 downto 0); + + signal buffer_clear : std_logic; + signal buffer_write : std_logic; + signal buffer_data : std_logic_vector(4 downto 0); + + signal seg_data : std_logic_vector(3 downto 0); + signal seg_off : std_logic; + signal seg_shift : std_logic; + signal seg_write : std_logic; + signal seg_clear : std_logic; + + signal on_off : std_logic; + + signal next_char : std_logic; + signal hex_char : std_logic_vector(4 downto 0); + + signal data_out : std_logic_vector(63 downto 0); + signal data_in : std_logic_vector(63 downto 0); + signal data_in_changed : std_logic; + + signal ack : std_logic; + + component scrolling_timer is + port( + clk : in std_logic; + rst : in std_logic; + cnt_start : in std_logic; + cnt_done : out std_logic; + cnt_value : in std_logic_vector(31 downto 0) + ); + end component; + + component scrolling_buffer + port( + clk : in std_logic; + rst : in std_logic; + buffer_clear : in std_logic; + buffer_write : in std_logic; + buffer_data : in std_logic_vector(4 downto 0); + next_char : in std_logic; + hex_char : out std_logic_vector(4 downto 0) + ); + end component; + + component scrolling_controller + port( + clk : in std_logic; + rst : in std_logic; + on_off : in std_logic; + cnt_start : out std_logic; + cnt_done : in std_logic; + next_char : out std_logic; + hex_char : in std_logic_vector(4 downto 0); + seg_data : out std_logic_vector(3 downto 0); + seg_off : out std_logic; + seg_shift : out std_logic; + seg_write : out std_logic; + seg_clear : out std_logic + ); + end component; + + component seven_segment_display is + port( + clk : in std_logic; + rst : in std_logic; + seg_data : in std_logic_vector(3 downto 0); + seg_off : in std_logic; + seg_shift : in std_logic; + seg_write : in std_logic; + seg_clear : in std_logic; + anodes : out std_logic_vector(7 downto 0); + cathodes : out std_logic_vector(7 downto 0) + ); + end component; + +begin + + timer: scrolling_timer + port map( + clk => clk, + rst => rst, + cnt_start => cnt_start, + cnt_done => cnt_done, + cnt_value => cnt_value + ); + + buf: scrolling_buffer + port map( + clk => clk, + rst => rst, + buffer_clear => buffer_clear, + buffer_write => buffer_write, + buffer_data => buffer_data, + next_char => next_char, + hex_char => hex_char + ); + + controller: scrolling_controller + port map( + clk => clk, + rst => rst, + on_off => on_off, + cnt_start => cnt_start, + cnt_done => cnt_done, + next_char => next_char, + hex_char => hex_char, + seg_data => seg_data, + seg_off => seg_off, + seg_shift => seg_shift, + seg_write => seg_write, + seg_clear => seg_clear + ); + + seven_segment: seven_segment_display + port map( + clk => clk, + rst => rst, + seg_data => seg_data, + seg_off => seg_off, + seg_shift => seg_shift, + seg_write => seg_write, + seg_clear => seg_clear, + + anodes => anodes, + cathodes => cathodes + ); + + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + ack <= '0'; + data_in <= (others => '0'); + data_in_changed <= '0'; + else + data_in <= (others => '0'); + data_in_changed <= '0'; + + if wslvi.stb = '1' and wslvi.cyc = '1' then + if wslvi.we='0' then + -- data_out will have the correct value + else + -- Write enable + data_in_changed <= '1'; + + if wslvi.adr(2) = '0' then + data_in(31 downto 0) <= dec_wb_dat(wslvi.sel,wslvi.dat); + else + data_in(63 downto 32) <= dec_wb_dat(wslvi.sel,wslvi.dat); + end if; + end if; + + if ack = '0' then + ack <= '1'; + else + ack <= '0'; + end if; + else + ack <= '0'; + end if; + end if; + end if; + end process; + + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + cnt_value <= (others => '0'); + buffer_write <= '0'; + buffer_clear <= '0'; + buffer_data <= (others => '0'); + on_off <= '0'; + else + buffer_write <= '0'; + buffer_clear <= '0'; + buffer_data <= (others => '0'); + on_off <= '0'; + + if data_in_changed = '1' and ack = '1' then + if wslvi.adr(2) = '1' then + cnt_value <= data_in(63 downto 32); + else + buffer_write <= data_in(24); + buffer_clear <= data_in(8); + buffer_data <= data_in(20 downto 16); + on_off <= data_in(0); + end if; + end if; + end if; + end if; + end process; + + data_out(31 downto 25) <= (others => '0'); + data_out(24) <= buffer_write; + data_out(23 downto 21) <= (others => '0'); + data_out(20 downto 16) <= buffer_data; + data_out(15 downto 9) <= (others => '0'); + data_out(8) <= buffer_clear; + data_out(7 downto 1) <= (others => '0'); + data_out(0) <= on_off; + + data_out(63 downto 32) <= cnt_value; + + wslvo.dat <= + data_out(31 downto 0) when wslvi.adr(2) = '0' else + data_out(63 downto 32) when wslvi.adr(2) = '1'; + + wslvo.ack <= ack; + wslvo.wbcfg <= wb_membar(memaddr, addrmask); + +end Behavioral; diff --git a/soc/peripheral/seven_segment_display.vhd b/soc/peripheral/seven_segment_display.vhd index e1d0779..09713e8 100644 --- a/soc/peripheral/seven_segment_display.vhd +++ b/soc/peripheral/seven_segment_display.vhd @@ -4,32 +4,24 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.lt16x32_global.all; -use work.wishbone.all; -use work.config.all; -entity wb_segment is - generic( - memaddr : generic_addr_type; --:= CFG_BADR_SEG; - addrmask : generic_mask_type --:= CFG_MADR_SEG; - ); +entity seven_segment_display is port( clk : in std_logic; rst : in std_logic; - wslvi : in wb_slv_in_type; - wslvo : out wb_slv_out_type; - + seg_data : in std_logic_vector(3 downto 0); + seg_off : in std_logic; + seg_shift : in std_logic; + seg_write : in std_logic; + seg_clear : in std_logic; anodes : out std_logic_vector(7 downto 0); cathodes : out std_logic_vector(7 downto 0) ); -end wb_segment; +end seven_segment_display; -architecture Behavioral of wb_segment is - - signal ack : std_logic; +architecture Behavioral of seven_segment_display is signal hex_register : std_logic_vector(63 downto 0); - signal data_out : std_logic_vector(63 downto 0); - signal hex : std_logic_vector(4 downto 0); signal timer_overflow : std_logic; @@ -69,40 +61,32 @@ begin rst => rst, timer_overflow => timer_overflow ); - - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - ack <= '0'; - data_out <= (others=>'0'); - hex_register <= (others=>'0'); - else - data_out <= (others=>'0'); - if wslvi.stb = '1' and wslvi.cyc = '1' then - if wslvi.we='0' then - data_out <= hex_register; - else - -- Write enable - if wslvi.adr(2) = '0' then - hex_register(31 downto 0) <= dec_wb_dat(wslvi.sel,wslvi.dat); - else -- wslvi.adr(2) = '1' - hex_register(63 downto 32) <= dec_wb_dat(wslvi.sel,wslvi.dat); - end if; - end if; - - if ack = '0' then - ack <= '1'; - else - ack <= '0'; - end if; - else - ack <= '0'; - end if; - end if; - end if; - end process; + process(clk) + begin + if clk'event and clk='1' then + if rst = '1' then + hex_register <= (others=>'0'); + else + -- No special care has to be taken to support + -- writing and shifting at the same time. + + if seg_shift = '1' then + hex_register(63 downto 56) <= (others => '0'); + hex_register(55 downto 0) <= hex_register(63 downto 8); + end if; + + if seg_write = '1' then + hex_register(59 downto 56) <= seg_data; + hex_register(60) <= not seg_off; -- unclear if this should only be set when write is 1 + end if; + + if seg_clear = '1' then + hex_register <= (others => '0'); + end if; + end if; + end if; + end process; process(clk) begin @@ -128,11 +112,4 @@ begin end if; end process; - wslvo.dat <= - data_out(31 downto 0) when wslvi.adr(2) = '0' else - data_out(63 downto 32) when wslvi.adr(2) = '1'; - - wslvo.ack <= ack; - wslvo.wbcfg <= wb_membar(memaddr, addrmask); - end Behavioral; diff --git a/soc/testbench/scrolling_top_tb.vhd b/soc/testbench/scrolling_top_tb.vhd new file mode 100644 index 0000000..c779d60 --- /dev/null +++ b/soc/testbench/scrolling_top_tb.vhd @@ -0,0 +1,136 @@ +-- See the file "LICENSE" for the full license governing this code. -- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY work; +USE work.lt16soc_peripherals.ALL; +USE work.wishbone.ALL; +USE work.wb_tp.ALL; +USE work.config.ALL; + +ENTITY scrolling_top_tb IS +END ENTITY; + +ARCHITECTURE sim OF scrolling_top_tb IS + + constant CLK_PERIOD : time := 10 ns; + + signal clk : std_logic := '0'; + signal rst : std_logic; + signal data : std_logic_vector(WB_PORT_SIZE-1 downto 0) := (others => '0'); + + signal anodes: std_logic_vector(7 downto 0); + signal cathodes : std_logic_vector(7 downto 0); + + signal slvi : wb_slv_in_type; + signal slvo : wb_slv_out_type; + +BEGIN + + SIM_SLV: wb_scrolling + generic map( + memaddr => CFG_BADR_SCR, + addrmask => CFG_MADR_SCR + ) + port map( + clk => clk, + rst => rst, + anodes => anodes, + cathodes => cathodes, + wslvi => slvi, + wslvo => slvo + ); + + clk_gen: process + begin + clk <= not clk; + wait for CLK_PERIOD / 2; + end process clk_gen; + + stimuli: process + begin + rst <= '1'; + wait for CLK_PERIOD; + rst <= '0'; + + wait for CLK_PERIOD; + + -- Set cnt_value + data <= x"00000100"; + generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4); + + wait for 2 ns; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"D"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '1'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"E"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '0'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"A"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '0'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"D"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '0'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + wait for 100 us; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"B"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '0'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"E"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '0'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"E"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '0'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + data <= (others => '0'); + data(24) <= '1'; -- buffer_write + data(20 downto 16) <= '0' & x"F"; -- buffer_data + data(8) <= '0'; -- buffer_clear + data(0) <= '0'; -- on_off + generate_sync_wb_single_write(slvi,slvo,clk,data); + wait for CLK_PERIOD; + + wait for 100 us; + + assert false report "Simulation terminated!" severity failure; + end process stimuli; + +END ARCHITECTURE; diff --git a/soc/testbench/segment_tb.vhd b/soc/testbench/segment_tb.vhd index 11c36eb..0cd5aca 100644 --- a/soc/testbench/segment_tb.vhd +++ b/soc/testbench/segment_tb.vhd @@ -18,26 +18,41 @@ ARCHITECTURE sim OF segment_tb IS signal clk : std_logic := '0'; signal rst : std_logic; - signal data : std_logic_vector(31 downto 0); + + signal seg_data : std_logic_vector(3 downto 0) := (others => '0'); + signal seg_off : std_logic := '0'; + signal seg_shift : std_logic := '0'; + signal seg_write : std_logic := '0'; + signal seg_clear : std_logic := '0'; signal anodes : std_logic_vector(7 downto 0); signal cathodes : std_logic_vector(7 downto 0); - signal slvi : wb_slv_in_type; - signal slvo : wb_slv_out_type; + component seven_segment_display is + port( + clk : in std_logic; + rst : in std_logic; + seg_data : in std_logic_vector(3 downto 0); + seg_off : in std_logic; + seg_shift : in std_logic; + seg_write : in std_logic; + seg_clear : in std_logic; + anodes : out std_logic_vector(7 downto 0); + cathodes : out std_logic_vector(7 downto 0) + ); + end component; BEGIN - SIM_SLV: wb_segment - generic map( - memaddr => CFG_BADR_SEG, - addrmask => CFG_MADR_SEG - ) + SIM_SLV: seven_segment_display port map( clk => clk, rst => rst, - wslvi => slvi, - wslvo => slvo, + seg_data => seg_data, + seg_off => seg_off, + seg_shift => seg_shift, + seg_write => seg_write, + seg_clear => seg_clear, anodes => anodes, cathodes => cathodes @@ -55,22 +70,71 @@ BEGIN wait for CLK_PERIOD; rst <= '0'; - data <= (others => '0'); - data(7 downto 0) <= "000" & "0" & x"A"; -- Unused & !Enable & Value - data(15 downto 8) <= "000" & "0" & x"B"; -- Unused & !Enable & Value - data(23 downto 16) <= "000" & "0" & x"C"; -- Unused & !Enable & Value - data(31 downto 24) <= "000" & "0" & x"D"; -- Unused & !Enable & Value - generate_sync_wb_single_write(slvi,slvo,clk,data); + seg_shift <= '0'; -- shift + seg_clear <= '0'; -- clear + seg_write <= '1'; -- write + seg_off <= '0'; -- off + seg_data <= x"F"; -- data + + wait for 1 us; - wait for 10 ns; - data <= (others => '0'); - data(7 downto 0) <= "000" & "0" & x"E"; -- Unused & !Enable & Value - data(15 downto 8) <= "000" & "0" & x"F"; -- Unused & !Enable & Value - data(23 downto 16) <= "000" & "0" & x"0"; -- Unused & !Enable & Value - data(31 downto 24) <= "000" & "0" & x"1"; -- Unused & !Enable & Value - generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4); + seg_shift <= '1'; -- shift + seg_clear <= '0'; -- clear + seg_write <= '0'; -- write + seg_off <= '0'; -- off + seg_data <= x"0"; -- data + + wait for CLK_PERIOD; + seg_shift <= '0'; - wait for 10 us; + wait for 1 us; + seg_shift <= '1'; -- shift + seg_clear <= '0'; -- clear + seg_write <= '1'; -- write + seg_off <= '0'; -- off + seg_data <= x"A"; -- data + + wait for CLK_PERIOD; + seg_shift <= '0'; + + wait for 1 us; + seg_shift <= '1'; -- shift + seg_clear <= '0'; -- clear + seg_write <= '1'; -- write + seg_off <= '0'; -- off + seg_data <= x"B"; -- data + + wait for CLK_PERIOD; + seg_shift <= '0'; + + wait for 1 us; + seg_shift <= '1'; -- shift + seg_clear <= '0'; -- clear + seg_write <= '1'; -- write + seg_off <= '0'; -- off + seg_data <= x"C"; -- + + wait for CLK_PERIOD; + seg_shift <= '0'; + + wait for 1 us; + seg_shift <= '1'; -- shift + seg_clear <= '0'; -- clear + seg_write <= '1'; -- write + seg_off <= '1'; -- off + seg_data <= x"0"; -- data + + wait for CLK_PERIOD; + seg_shift <= '0'; + + wait for 1 us; + seg_shift <= '0'; -- shift + seg_clear <= '1'; -- clear + seg_write <= '0'; -- write + seg_off <= '0'; -- off + seg_data <= x"0"; -- data + + wait for 1 us; assert false report "Simulation terminated!" severity failure; end process stimuli;