Implement scrolling_buffer and testbench for it
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83
soc/peripheral/scrolling_buffer.vhd
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83
soc/peripheral/scrolling_buffer.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity scrolling_buffer is
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port(
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clk : in std_logic;
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rst : in std_logic;
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buffer_clear : in std_logic;
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buffer_write : in std_logic;
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buffer_data : in std_logic_vector(4 downto 0);
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next_char : in std_logic;
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hex_char : out std_logic_vector(4 downto 0)
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);
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end entity scrolling_buffer;
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architecture Behavioral of scrolling_buffer is
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constant BUFFER_SIZE : integer := 16;
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type ring_buffer_type is array (0 to BUFFER_SIZE - 1) of std_logic_vector(4 downto 0);
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signal ptr_write : integer range 0 to BUFFER_SIZE - 1;
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signal ptr_read : integer range 0 to BUFFER_SIZE - 1;
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signal ptr_last : integer range -1 to BUFFER_SIZE - 1;
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signal ring_buffer : ring_buffer_type;
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begin
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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ptr_last <= -1;
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ptr_write <= 0;
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ring_buffer <= (others => (others => '0'));
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else
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if buffer_write = '1' then
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ring_buffer(ptr_write) <= buffer_data;
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if ptr_last /= BUFFER_SIZE - 1 then
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ptr_last <= ptr_write;
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end if;
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if ptr_write = BUFFER_SIZE - 1 then
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ptr_write <= 0;
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else
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ptr_write <= ptr_write + 1;
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end if;
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elsif buffer_clear = '1' then
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ptr_last <= -1;
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end if;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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ptr_read <= 0;
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hex_char <= (others => '0');
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else
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hex_char <= (others => '0');
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if next_char = '1' then
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if ptr_last = -1 then -- Special case
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hex_char <= (others => '0');
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else
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hex_char <= ring_buffer(ptr_read);
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if ptr_read = ptr_last then
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ptr_read <= 0;
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else
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ptr_read <= ptr_read + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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121
soc/testbench/scrolling_buffer_tb.vhd
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121
soc/testbench/scrolling_buffer_tb.vhd
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-- See the file "LICENSE" for the full license governing this code. --
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY work;
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USE work.lt16soc_peripherals.ALL;
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ENTITY scrolling_buffer_tb IS
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END ENTITY;
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ARCHITECTURE sim OF scrolling_buffer_tb IS
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constant CLK_PERIOD : time := 10 ns;
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signal rst : std_logic;
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signal clk : std_logic := '0';
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signal buffer_clear : std_logic := '0';
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signal buffer_write : std_logic := '0';
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signal buffer_data : std_logic_vector(4 downto 0) := (others => '0');
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signal next_char : std_logic := '0';
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signal hex_char : std_logic_vector(4 downto 0);
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component scrolling_buffer
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port(
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clk : in std_logic;
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rst : in std_logic;
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buffer_clear : in std_logic;
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buffer_write : in std_logic;
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buffer_data : in std_logic_vector(4 downto 0);
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next_char : in std_logic;
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hex_char : out std_logic_vector(4 downto 0)
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);
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end component;
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BEGIN
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buf: scrolling_buffer
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port map(
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clk => clk,
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rst => rst,
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buffer_clear => buffer_clear,
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buffer_write => buffer_write,
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buffer_data => buffer_data,
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next_char => next_char,
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hex_char => hex_char
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);
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clk_gen: process
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begin
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clk <= not clk;
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wait for CLK_PERIOD/2;
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end process clk_gen;
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stimuli: process
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begin
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rst <= '1';
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wait for CLK_PERIOD;
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rst <= '0';
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wait for CLK_PERIOD;
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buffer_data <= "00001";
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buffer_write <= '1';
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wait for CLK_PERIOD;
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buffer_data <= "01011";
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wait for CLK_PERIOD;
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buffer_write <= '0';
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wait for CLK_PERIOD;
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buffer_data <= "01001";
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buffer_write <= '1';
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wait for CLK_PERIOD;
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buffer_data <= "00000";
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buffer_write <= '0';
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wait for CLK_PERIOD;
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next_char <= '1';
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wait for CLK_PERIOD;
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assert hex_char = "00001" severity failure;
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wait for CLK_PERIOD;
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assert hex_char = "01011" severity failure;
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wait for CLK_PERIOD;
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assert hex_char = "01001" severity failure;
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wait for CLK_PERIOD;
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next_char <= '0';
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assert hex_char = "00001" severity failure; -- special case
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wait for CLK_PERIOD * 3;
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-- Write buffer full
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buffer_data <= "11111";
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buffer_write <= '1';
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wait for CLK_PERIOD * 16;
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buffer_data <= "00000";
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buffer_write <= '0';
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wait for CLK_PERIOD;
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next_char <= '1';
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wait for CLK_PERIOD * 8;
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buffer_clear <= '1';
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wait for CLK_PERIOD;
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buffer_clear <= '0';
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wait for CLK_PERIOD * 8;
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assert false report "Simulation terminated!" severity failure;
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end process stimuli;
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END ARCHITECTURE;
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