diff --git a/programs/project.prog b/programs/project.prog index 980c34b..35d6ef8 100644 --- a/programs/project.prog +++ b/programs/project.prog @@ -46,10 +46,10 @@ can_output_control_addr: .word 0x000F0108 // CAN Constants acceptance_code: .word 0x00 acceptance_mask: .word 0xFF -// btr0: .word 0x45 // for Real board -// btr1: .word 0x16 // for Real board -btr0: .word 0x80 -btr1: .word 0x48 +btr0: .word 0x45 // for Real board +btr1: .word 0x16 // for Real board +// btr0: .word 0x80 +// btr1: .word 0x48 output_control: .word 0x02 control: .word 0xFE rx_interrupt_mask: .word 0x01 diff --git a/soc/top/external_can.vhd b/soc/top/external_can.vhd new file mode 100644 index 0000000..c6741af --- /dev/null +++ b/soc/top/external_can.vhd @@ -0,0 +1,129 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01/04/2023 01:55:04 PM +-- Design Name: +-- Module Name: internal_can - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity external_can is +port( + -- clock signal + clk : in std_logic; + -- external reset button + rst : in std_logic; + + led : out std_logic_vector(7 downto 0); + + btn : in std_logic_vector(4 downto 0); + sw : in std_logic_vector(15 downto 0); + + anodes : out std_logic_vector(7 downto 0); + cathodes : out std_logic_vector(7 downto 0); + + -- pmod + pmod_rxd : in std_logic_vector(1 downto 0); + pmod_txd : out std_logic_vector(1 downto 0); + pmod_de : out std_logic_vector(1 downto 0); + pmod_re_n : out std_logic_vector(1 downto 0) +); +end entity; + +architecture Behavioral of external_can is + COMPONENT lt16soc_top IS + generic( + programfilename : string := "../../programs/project.ram" + ); + port( + clk : in std_logic; + rst : in std_logic; + led : out std_logic_vector(7 downto 0); + btn : in std_logic_vector(4 downto 0); + sw : in std_logic_vector(15 downto 0); + anodes : out std_logic_vector(7 downto 0); + cathodes : out std_logic_vector(7 downto 0); + can_rx_i : in std_logic; + can_tx_o : out std_logic + ); + END COMPONENT; + + signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0'); + signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0'); + + signal anodes_cpy : std_logic_vector(7 downto 0); + signal cathodes_cpy : std_logic_vector(7 downto 0); + + signal led_cpy : std_logic_vector(7 downto 0); + + signal tx : std_logic_vector(1 downto 0); + + signal rst_n : std_logic; +begin + + soc0: lt16soc_top + generic map( + programfilename => "../../programs/project.ram" + ) + port map( + clk=>clk, + rst=>rst, + led=>led, + btn=>btn, + sw=>sw, + anodes=>anodes_cpy, + cathodes=>cathodes_cpy, + can_rx_i=>pmod_rxd(0), + can_tx_o=>tx(0) + ); + + soc1: lt16soc_top + generic map( + programfilename => "../../programs/project.ram" + ) + port map( + clk=>clk, + rst=>rst, + led=>led_cpy, + btn=>btn_cpy, + sw=>sw_cpy, + anodes=>anodes, + cathodes=>cathodes, + can_rx_i=>pmod_rxd(1), + can_tx_o=>tx(1) + ); + + -- TODO: für pmod !read enable auf low setzen + pmod_re_n <= (others => '0'); + -- pmod_de <= (others => '1'); + + pmod_de <= not tx; + pmod_txd <= tx; + + rst_n <= not rst; + +end Behavioral; diff --git a/soc/top/internal_can.vhd b/soc/top/internal_can.vhd new file mode 100644 index 0000000..ed51564 --- /dev/null +++ b/soc/top/internal_can.vhd @@ -0,0 +1,143 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01/04/2023 01:55:04 PM +-- Design Name: +-- Module Name: internal_can - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity internal_can is +port( + -- clock signal + clk : in std_logic; + -- external reset button + rst : in std_logic; + + led : out std_logic_vector(7 downto 0); + + btn : in std_logic_vector(4 downto 0); + sw : in std_logic_vector(15 downto 0); + + anodes : out std_logic_vector(7 downto 0); + cathodes : out std_logic_vector(7 downto 0); + + can_rx_i : in std_logic; + can_tx_o : out std_logic +); +end entity; + +architecture Behavioral of internal_can is + COMPONENT lt16soc_top IS + generic( + programfilename : string := "../../programs/project.ram" + ); + port( + clk : in std_logic; + rst : in std_logic; + led : out std_logic_vector(7 downto 0); + btn : in std_logic_vector(4 downto 0); + sw : in std_logic_vector(15 downto 0); + anodes : out std_logic_vector(7 downto 0); + cathodes : out std_logic_vector(7 downto 0); + can_rx_i : in std_logic; + can_tx_o : out std_logic + ); + END COMPONENT; + + component phys_can_sim + generic( + peer_num : integer ); + port( + rst : in std_logic; + rx_vector : out std_logic_vector(peer_num - 1 downto 0); + tx_vector : in std_logic_vector(peer_num - 1 downto 0) ); + end component phys_can_sim; + + constant peer_num_inst : integer := 2; + signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0); + signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0); + + signal rst_n : std_logic; + + signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0'); + signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0'); + + signal anodes_cpy : std_logic_vector(7 downto 0); + signal cathodes_cpy : std_logic_vector(7 downto 0); + + signal led_cpy : std_logic_vector(7 downto 0); +begin + + soc0: lt16soc_top + generic map( + programfilename => "../../programs/project.ram" + ) + port map( + clk=>clk, + rst=>rst, + led=>led, + btn=>btn, + sw=>sw, + anodes=>anodes, + cathodes=>cathodes, + can_rx_i=>rx_vector(0), + can_tx_o=>tx_vector(0) + ); + + soc1: lt16soc_top + generic map( + programfilename => "../../programs/project.ram" + ) + port map( + clk=>clk, + rst=>rst, + led=>led_cpy, + btn=>btn_cpy, + sw=>sw_cpy, + anodes=>anodes_cpy, + cathodes=>cathodes_cpy, + can_rx_i=>rx_vector(1), + can_tx_o=>tx_vector(1) + ); + + can_interconnect : phys_can_sim + generic map( + peer_num => peer_num_inst + ) + port map( + rst => rst_n, + rx_vector => rx_vector, + tx_vector => tx_vector + ); + + rst_n <= not rst; + can_tx_o <= tx_vector(1); + + -- TODO: für pmod !read enable auf low setzen + +end Behavioral; diff --git a/soc/top/top.xdc b/soc/top/top.xdc index f1a2f7e..b0c57e2 100644 --- a/soc/top/top.xdc +++ b/soc/top/top.xdc @@ -81,20 +81,20 @@ set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btn[4] ##Pmod Headers ##Pmod Header JA -set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { can_rx_i }]; #IO_L20N_T3_A19_15 Sch=ja[1] -set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { can_tx_o }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { pmod_re_n[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { pmod_txd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { pmod_rxd[0] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { pmod_de[0] }]; #IO_L18N_T2_A23_15 Sch=ja[4] #set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] #set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] #set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] #set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] ##Pmod Header JB -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { pmod_re_n[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { pmod_txd[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { pmod_rxd[1] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { pmod_de[1] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] #set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] #set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]