First working switches testbench

soc/peripheral/peripherals.vhd

@@ -26,6 +26,22 @@ package lt16soc_peripherals is
 	);
 	end component;
 
+	component wb_switches is
+	generic(
+		memaddr		:	generic_addr_type; --:= CFG_BADR_LED;
+		addrmask	:	generic_mask_type --:= CFG_MADR_LED;
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		wslvi	:	in	wb_slv_in_type;
+		wslvo	:	out	wb_slv_out_type;
+
+        buttons : in std_logic_vector(4 downto 0);
+        switches : in std_logic_vector(15 downto 0)
+	);
+	end component;
+
 end lt16soc_peripherals;
 
 package body lt16soc_peripherals is

soc/peripheral/switches.vhd

@@ -7,7 +7,7 @@ use work.lt16x32_global.all;
 use work.wishbone.all;
 use work.config.all;
 
-entity wb_led is
+entity wb_switches is
 	generic(
 		memaddr		:	generic_addr_type; --:= CFG_BADR_LED;
 		addrmask	:	generic_mask_type --:= CFG_MADR_LED;
@@ -19,11 +19,11 @@ entity wb_led is
 		wslvo	:	out	wb_slv_out_type;
 
         buttons : in std_logic_vector(4 downto 0);
-        switches : in std_logic_vector(15 downto 0);
+        switches : in std_logic_vector(15 downto 0)
 	);
-end wb_led;
+end wb_switches;
 
-architecture Behavioral of wb_led is
+architecture Behavioral of wb_switches is
 
 	signal data : std_logic_vector(20 downto 0);
 	signal ack	: std_logic;
@@ -35,7 +35,7 @@ begin
 		if clk'event and clk='1' then
 			if rst = '1' then
 				ack		<= '0';
-				data	<= x"0F";
+				data	<= (others=>'0');
 			else
 				if wslvi.stb = '1' and wslvi.cyc = '1' then
                     data(15 downto 0) <= switches;

soc/testbench/switches_tb.vhd

@@ -0,0 +1,71 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY work;
+USE work.lt16soc_peripherals.ALL;
+USE work.wishbone.ALL;
+USE work.wb_tp.ALL;
+USE work.config.ALL;
+
+ENTITY switches_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF switches_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+	signal data	: std_logic_vector(WB_PORT_SIZE-1 downto 0);
+	
+    signal buttons: std_logic_vector(4 downto 0);
+    signal switches : std_logic_vector(15 downto 0);
+
+	signal slvi	: wb_slv_in_type;
+	signal slvo	: wb_slv_out_type;
+
+BEGIN
+
+	SIM_SLV: wb_switches
+		generic map(
+			memaddr		=> CFG_BADR_LED,
+			addrmask	=> CFG_MADR_LED
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst,
+			buttons => buttons,
+			switches => switches,
+			wslvi	=> slvi,
+			wslvo	=> slvo
+		);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '1';
+		wait for CLK_PERIOD;
+		rst	<= '0';
+		buttons <= "00110";
+		switches <= "1001000101010111";
+		wait for CLK_PERIOD;
+		
+        data	<= (others => '0');
+		generate_sync_wb_single_read(slvi,slvo,clk,data);
+		
+		wait for 2 ns;
+		
+		data	<= (others => '0');
+		generate_sync_wb_single_read(slvi,slvo,clk,data);
+
+		wait;
+	end process stimuli;
+
+END ARCHITECTURE;