Integrate CAN controller and implement switches interrupt

soc/testbench/switches_tb.vhd

@@ -23,6 +23,8 @@ ARCHITECTURE sim OF switches_tb IS
     signal buttons: std_logic_vector(4 downto 0);
     signal switches : std_logic_vector(15 downto 0);
 
+    signal interrupt : std_logic;
+
 	signal slvi	: wb_slv_in_type;
 	signal slvo	: wb_slv_out_type;
 
@@ -38,6 +40,7 @@ BEGIN
 			rst		=> rst,
 			buttons => buttons,
 			switches => switches,
+            interrupt => interrupt,
 			wslvi	=> slvi,
 			wslvo	=> slvo
 		);
@@ -74,6 +77,31 @@ BEGIN
 		generate_sync_wb_single_read(slvi,slvo,clk,data, SIZE => "01"); -- Half word
 		
 		wait for 100 ns;
+		
+		buttons <= "00000";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00100";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00000";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00000";
+		switches <= x"DAAD";
+		
+		wait for 50ns;
+		buttons <= "01000";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
+		buttons <= "00010";
+		switches <= x"DEAD";
+		
+		wait for 50ns;
 
 		assert false report "Simulation terminated!" severity failure;
 	end process stimuli;