Integrate CAN controller and implement switches interrupt

This commit is contained in:
2022-12-07 22:35:29 +01:00
parent 2e03702047
commit 7af2c51d61
17 changed files with 346 additions and 22 deletions

View File

@@ -12,6 +12,22 @@ use work.config.all;
package lt16soc_peripherals is
component can_vhdl_top is
generic(
memaddr : generic_addr_type;
addrmask : generic_mask_type
);
port(
clk : in std_logic;
rstn : in std_logic;
wbs_i : in wb_slv_in_type;
wbs_o : out wb_slv_out_type;
rx_i : in std_logic;
tx_o : out std_logic;
irq_on : out std_logic
);
end component can_vhdl_top;
component wb_led is
generic(
memaddr : generic_addr_type;-- := CFG_BADR_LED;
@@ -38,7 +54,9 @@ package lt16soc_peripherals is
wslvo : out wb_slv_out_type;
buttons : in std_logic_vector(4 downto 0);
switches : in std_logic_vector(15 downto 0)
switches : in std_logic_vector(15 downto 0);
interrupt : out std_logic
);
end component;

View File

@@ -19,7 +19,9 @@ entity wb_switches is
wslvo : out wb_slv_out_type;
buttons : in std_logic_vector(4 downto 0);
switches : in std_logic_vector(15 downto 0)
switches : in std_logic_vector(15 downto 0);
interrupt : out std_logic
);
end wb_switches;
@@ -28,6 +30,8 @@ architecture Behavioral of wb_switches is
signal data : std_logic_vector(20 downto 0);
signal ack : std_logic;
signal old_input : std_logic_vector(20 downto 0);
begin
process(clk)
@@ -55,6 +59,26 @@ begin
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if rst = '1' then
interrupt <= '0';
old_input <= (others => '0');
else
if buttons & switches /= old_input
then
interrupt <= '1';
else
interrupt <= '0';
end if;
old_input(15 downto 0) <= switches;
old_input(20 downto 16) <= buttons;
end if;
end if;
end process;
wslvo.dat(20 downto 0) <= data;
wslvo.dat(31 downto 21) <= (others=>'0');