Add seven-segments-display program

programs/segments_test.prog

@@ -0,0 +1,89 @@
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+number_array0:
+    .word 0x03020100
+number_array1:
+    .word 0x07060504
+number_array2:
+    .word 0x0B0A0908
+number_array3:
+    .word 0x0F0E0D0C
+
+segment_addr0: .word 0x000F00A0
+segment_addr1: .word 0x000F00A4
+// w_cnt_top:  .word 0x1FC000
+w_cnt_top:    .word 0x100 //for simulation only
+
+
+infamous_pattern0:
+    .word 0x0D0E0A0D
+infamous_pattern1:
+    .word 0x0B0E0E0F
+
+main:
+    ldr r8, >w_cnt_top
+
+number_loop:
+    // First 4
+    ldr r4, >number_array0
+    ldr r0, >segment_addr0
+    st32 r0, r4
+
+    // Second 4
+    ldr r4, >number_array1
+    ldr r0, >segment_addr1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // First 4
+    ldr r4, >number_array2
+    ldr r0, >segment_addr0
+    st32 r0, r4
+
+    // Second 4
+    ldr r4, >number_array3
+    ldr r0, >segment_addr1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    // 0xDEADBEEF pattern:
+
+    // First 4
+    ldr r4, >infamous_pattern0
+    ldr r0, >segment_addr0
+    st32 r0, r4
+
+    // Second 4
+    ldr r4, >infamous_pattern1
+    ldr r0, >segment_addr1
+    st32 r0, r4
+
+    call >wait
+    nop
+
+    br always >number_loop
+    nop
+
+
+//subroutine to iterate until counter overflow
+wait:
+    clr r7                //inititalize inner counter
+    inc_i:
+    cmp neq r7,r8
+    br true >inc_i        //if i=cnt_top
+    addi r7,1
+    ret                    //else
+    nop

soc/testbench/warmup3.vhd

@@ -0,0 +1,65 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY warmup3_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF warmup3_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/segments_test.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0)
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 5000*CLK_PERIOD;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/top/top.vhd

@@ -14,7 +14,7 @@ use work.lt16soc_peripherals.all;
 
 entity lt16soc_top is
 generic(
-	programfilename : string := "../../programs/timer_blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
+	programfilename : string := "../../programs/segments_test.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
 );
 port(
 	-- clock signal
@@ -211,7 +211,7 @@ begin
 		)
 		port map(
 			clk		=> clk,
-			rst		=> rst,
+			rst		=> rst_gen,
 			wslvi	=> slvi(CFG_SEG),
 			wslvo	=> slvo(CFG_SEG),