From 653e0d3a44ea9a6e4acd4f0298d7f415db8766bc Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Sat, 19 Nov 2022 16:15:39 +0100 Subject: [PATCH] Fix read interface for seven segment --- soc/peripheral/seven_segment_display_adv.vhd | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/soc/peripheral/seven_segment_display_adv.vhd b/soc/peripheral/seven_segment_display_adv.vhd index b7ff95a..9fb2170 100644 --- a/soc/peripheral/seven_segment_display_adv.vhd +++ b/soc/peripheral/seven_segment_display_adv.vhd @@ -28,7 +28,7 @@ architecture Behavioral of wb_segment_adv is signal ack : std_logic; signal hex_register : std_logic_vector(63 downto 0); - signal data_out : std_logic_vector(63 downto 0); + signal data_out : std_logic_vector(31 downto 0); signal data_in : std_logic_vector(31 downto 0); signal data_in_changed : std_logic; @@ -64,8 +64,8 @@ begin ); timer: simple_timer - -- generic map (timer_start => x"00000008") -- for simulation - generic map (timer_start => x"00000F00") -- for board + generic map (timer_start => x"00000008") -- for simulation + -- generic map (timer_start => x"00000F00") -- for board port map( clk => clk, rst => rst, @@ -81,13 +81,13 @@ begin data_in <= (others=>'0'); data_in_changed <= '0'; else - data_out <= (others=>'0'); + data_out <= (others=>'0'); data_in <= (others=>'0'); data_in_changed <= '0'; if wslvi.stb = '1' and wslvi.cyc = '1' then if wslvi.we='0' then - data_out <= hex_register; + -- data_out will stay 0 else -- Write enable data_in <= dec_wb_dat(wslvi.sel,wslvi.dat); @@ -169,9 +169,7 @@ begin end if; end process; - wslvo.dat <= - data_out(31 downto 0) when wslvi.adr(2) = '0' else - data_out(63 downto 32) when wslvi.adr(2) = '1'; + wslvo.dat <= data_out; wslvo.ack <= ack; wslvo.wbcfg <= wb_membar(memaddr, addrmask);