First implementation of the switches module

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2022-11-05 17:16:40 +01:00
parent cd6a782b2c
commit 233cd9014b

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_global.all;
use work.wishbone.all;
use work.config.all;
entity wb_led is
generic(
memaddr : generic_addr_type; --:= CFG_BADR_LED;
addrmask : generic_mask_type --:= CFG_MADR_LED;
);
port(
clk : in std_logic;
rst : in std_logic;
wslvi : in wb_slv_in_type;
wslvo : out wb_slv_out_type;
buttons : in std_logic_vector(4 downto 0);
switches : in std_logic_vector(15 downto 0);
);
end wb_led;
architecture Behavioral of wb_led is
signal data : std_logic_vector(20 downto 0);
signal ack : std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
if rst = '1' then
ack <= '0';
data <= x"0F";
else
if wslvi.stb = '1' and wslvi.cyc = '1' then
data(15 downto 0) <= switches;
data(20 downto 16) <= buttons;
if ack = '0' then
ack <= '1';
else
ack <= '0';
end if;
else
ack <= '0';
end if;
end if;
end if;
end process;
wslvo.dat(20 downto 0) <= data;
wslvo.dat(31 downto 21) <= (others=>'0');
wslvo.ack <= ack;
wslvo.wbcfg <= wb_membar(memaddr, addrmask);
end Behavioral;