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-- Company: 
-- Engineer: 
-- 
-- Create Date: 01/04/2023 01:55:04 PM
-- Design Name: 
-- Module Name: internal_can - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity internal_can is
port(
	-- clock signal
	clk		: in  std_logic;
	-- external reset button
	rst		: in std_logic;
	
	led		: out std_logic_vector(7 downto 0);
	
	btn : in std_logic_vector(4 downto 0);
	sw : in std_logic_vector(15 downto 0);
	
	anodes : out std_logic_vector(7 downto 0);
    cathodes : out std_logic_vector(7 downto 0);

    can_rx_i : in std_logic;
    can_tx_o : out std_logic
);
end entity;

architecture Behavioral of internal_can is
	COMPONENT lt16soc_top IS
		generic(
			programfilename : string := "../../programs/project.ram"
		);
		port(
			clk		: in  std_logic;
			rst		: in std_logic;
			led		: out std_logic_vector(7 downto 0);
			btn : in std_logic_vector(4 downto 0);
	        sw : in std_logic_vector(15 downto 0);
            anodes : out std_logic_vector(7 downto 0);
            cathodes : out std_logic_vector(7 downto 0);
            can_rx_i : in std_logic;
            can_tx_o : out std_logic
		);
	END COMPONENT;
	
    component phys_can_sim 
		generic(
			peer_num : integer );
		port(
			rst : in std_logic;
			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
	end component phys_can_sim;
	
    constant peer_num_inst : integer := 2;
	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
	
	signal rst_n : std_logic;
	
    signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0');
	signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0');
	
	signal anodes_cpy : std_logic_vector(7 downto 0);
    signal cathodes_cpy : std_logic_vector(7 downto 0);
    
    signal led_cpy : std_logic_vector(7 downto 0);
begin

	soc0: lt16soc_top
    generic map(
        programfilename => "../../programs/project.ram"
    )
    port map(
		clk=>clk,
		rst=>rst,
		led=>led,
		btn=>btn,
		sw=>sw,
        anodes=>anodes,
        cathodes=>cathodes,
        can_rx_i=>rx_vector(0),
        can_tx_o=>tx_vector(0)
	);

    soc1: lt16soc_top
    generic map(
        programfilename => "../../programs/project.ram"
    )
    port map(
		clk=>clk,
		rst=>rst,
		led=>led_cpy,
		btn=>btn_cpy,
		sw=>sw_cpy,
        anodes=>anodes_cpy,
        cathodes=>cathodes_cpy,
        can_rx_i=>rx_vector(1),
        can_tx_o=>tx_vector(1)
	);
	
    can_interconnect : phys_can_sim
    generic map(
        peer_num => peer_num_inst
    )
    port map(
        rst => rst_n,
        rx_vector => rx_vector,
        tx_vector => tx_vector
    );
    
    rst_n <= not rst;
    can_tx_o <= tx_vector(1);
    
    -- TODO: für pmod !read enable auf low setzen

end Behavioral;
