-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

use work.wishbone.all;
use work.config.all;
use work.lt16soc_memories.all;
use work.lt16soc_peripherals.all;

ENTITY project_tb IS
END ENTITY;

ARCHITECTURE sim OF project_tb IS

	constant CLK_PERIOD : time := 10 ns;

	signal clk 	: std_logic := '0';
	signal rst	: std_logic;

	signal led	: std_logic_vector(7 downto 0);
    signal btn : std_logic_vector(4 downto 0) := (others => '0');
    signal sw : std_logic_vector(15 downto 0) := (others => '0');
    signal anodes : std_logic_vector(7 downto 0);
    signal cathodes : std_logic_vector(7 downto 0);
    
	constant peer_num_inst : integer := 3;
	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);

	COMPONENT lt16soc_top IS
		generic(
			programfilename : string := "../../programs/project.ram"
		);
		port(
			clk		: in  std_logic;
			rst		: in std_logic;
			led		: out std_logic_vector(7 downto 0);
			btn : in std_logic_vector(4 downto 0);
	        sw : in std_logic_vector(15 downto 0);
            anodes : out std_logic_vector(7 downto 0);
            cathodes : out std_logic_vector(7 downto 0);
            can_rx_i : in std_logic;
            can_tx_o : out std_logic
		);
	END COMPONENT;
	
    component phys_can_sim 
		generic(
			peer_num : integer );
		port(
			rst : in std_logic;
			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
	end component phys_can_sim;

BEGIN

	dut: lt16soc_top port map(
		clk=>clk,
		rst=>rst,
		led=>led,
		btn=>btn,
		sw=>sw,
        anodes=>anodes,
        cathodes=>cathodes,
        can_rx_i=>rx_vector(0),
        can_tx_o=>tx_vector(0)
	);
	 
    can_inst_2 : can_vhdl_top
    generic map(
        memaddr=>CFG_BADR_MEM,
        addrmask=>CFG_MADR_FULL
    )
    port map(
        clk	=> clk,
        rstn	=> rst,
        wbs_i	=> wbs_i2,
        wbs_o	=> wbs_o2,
        rx_i	=> rx_vector(1),
        tx_o	=> tx_vector(1),
        irq_on	=> irq_on2
    );
        
    can_interconnect : phys_can_sim
    generic map(
        peer_num => 2
    )
    port map(
        rst => rst,
        rx_vector => can_rx,
        tx_vector => can_tx
    );

	clk_gen: process
	begin
		clk	<= not clk;
		wait for CLK_PERIOD/2;
	end process clk_gen;

	stimuli: process
	begin
		rst	<= '0';
		wait for CLK_PERIOD;
		rst	<= '1';
		wait for 300us;
		assert false report "Simulation terminated!" severity failure;
	end process stimuli;

END ARCHITECTURE;
