library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simple_timer is
    generic(
        timer_start : std_logic_vector (31 downto 0)
    );
    port(
        clk : in std_logic;
        rst : in std_logic;
        timer_overflow : out std_logic
    );
end entity simple_timer;

architecture Behavioral of simple_timer is

	signal counter : integer range 1 to to_integer(unsigned(timer_start));
    signal overflow : std_logic;

begin

	process(clk)
	begin
		if clk'event and clk='1' then
			if rst = '1' then
				counter <= to_integer(unsigned(timer_start));
			else
                overflow <= '0';

				if counter = 1 then
                    counter <= to_integer(unsigned(timer_start));
                    overflow <= '1';
                else
                    counter <= counter - 1;
                end if;
			end if;
		end if;
	end process;

    timer_overflow <= overflow;

end Behavioral;
