-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;
USE work.lt16soc_peripherals.ALL;
USE work.wishbone.ALL;
USE work.wb_tp.ALL;
USE work.config.ALL;

ENTITY segment_tb IS
END ENTITY;

ARCHITECTURE sim OF segment_tb IS

	constant CLK_PERIOD : time := 10 ns;

	signal clk 	: std_logic := '0';
	signal rst	: std_logic;
	signal data	: std_logic_vector(31 downto 0);
	
    signal anodes : std_logic_vector(7 downto 0);
    signal cathodes : std_logic_vector(7 downto 0);

	signal slvi	: wb_slv_in_type;
	signal slvo	: wb_slv_out_type;

BEGIN

	SIM_SLV: wb_segment
		generic map(
			memaddr		=> CFG_BADR_SEG,
			addrmask	=> CFG_MADR_SEG
		)
		port map(
			clk		=> clk,
			rst		=> rst,
			wslvi	=> slvi,
			wslvo	=> slvo,

            anodes => anodes,
            cathodes => cathodes
		);

	clk_gen: process
	begin
		clk	<= not clk;
		wait for CLK_PERIOD/2;
	end process clk_gen;

	stimuli: process
	begin
		rst	<= '1';
		wait for CLK_PERIOD;
		rst	<= '0';

        data <= (others => '0');
        data(7 downto 0) <= "000" & "0" & x"A"; -- Unused & !Enable & Value
        data(15 downto 8) <= "000" & "0" & x"B"; -- Unused & !Enable & Value
        data(23 downto 16) <= "000" & "0" & x"C"; -- Unused & !Enable & Value
        data(31 downto 24) <= "000" & "0" & x"D"; -- Unused & !Enable & Value
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		
        wait for 10 ns;
        data <= (others => '0');
        data(7 downto 0) <= "000" & "0" & x"E"; -- Unused & !Enable & Value
        data(15 downto 8) <= "000" & "0" & x"F"; -- Unused & !Enable & Value
        data(23 downto 16) <= "000" & "0" & x"0"; -- Unused & !Enable & Value
        data(31 downto 24) <= "000" & "0" & x"1"; -- Unused & !Enable & Value
        generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4);
		
		wait for 10 us;

		assert false report "Simulation terminated!" severity failure;
	end process stimuli;

END ARCHITECTURE;
