-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;
USE work.lt16soc_peripherals.ALL;
USE work.wishbone.ALL;
USE work.wb_tp.ALL;
USE work.config.ALL;

ENTITY switches_tb IS
END ENTITY;

ARCHITECTURE sim OF switches_tb IS

	constant CLK_PERIOD : time := 10 ns;

	signal clk 	: std_logic := '0';
	signal rst	: std_logic;
	signal data	: std_logic_vector(WB_PORT_SIZE-1 downto 0);
	
    signal buttons: std_logic_vector(4 downto 0);
    signal switches : std_logic_vector(15 downto 0);

	signal slvi	: wb_slv_in_type;
	signal slvo	: wb_slv_out_type;

BEGIN

	SIM_SLV: wb_switches
		generic map(
			memaddr		=> CFG_BADR_LED,
			addrmask	=> CFG_MADR_LED
		)
		port map(
			clk		=> clk,
			rst		=> rst,
			buttons => buttons,
			switches => switches,
			wslvi	=> slvi,
			wslvo	=> slvo
		);

	clk_gen: process
	begin
		clk	<= not clk;
		wait for CLK_PERIOD/2;
	end process clk_gen;

	stimuli: process
	begin
		rst	<= '1';
		wait for CLK_PERIOD;
		rst	<= '0';
		buttons <= "00110";
		switches <= "1001000101010111";
		wait for CLK_PERIOD;
		
		generate_sync_wb_single_read(slvi,slvo,clk,data);
		
		wait for 2 ns;
		
		generate_sync_wb_single_read(slvi,slvo,clk,data);
		
		buttons <= "11011";
		switches <= x"DEAD";
        wait for 10 ns;
		
		generate_sync_wb_single_read(slvi,slvo,clk,data, SIZE => "00"); -- Single byte
		
        wait for 10 ns;
		
		generate_sync_wb_single_read(slvi,slvo,clk,data, SIZE => "01"); -- Half word
		
		wait for 100 ns;

		assert false report "Simulation terminated!" severity failure;
	end process stimuli;

END ARCHITECTURE;
