<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
   <wave_state>
   </wave_state>
   <db_ref_list>
      <db_ref path="C:/msys/1.0/home/Ben/hiwi/esysoc/memdiv_tb_isim_beh.wdb" id="1" type="auto">
         <top_modules>
            <top_module name="config" />
            <top_module name="lt16x32_global" />
            <top_module name="lt16x32_internal" />
            <top_module name="memdiv_tb" />
            <top_module name="numeric_std" />
            <top_module name="std_logic_1164" />
            <top_module name="textio" />
            <top_module name="wishbone" />
         </top_modules>
      </db_ref>
   </db_ref_list>
   <WVObjectSize size="8" />
   <wvobject fp_name="/memdiv_tb/clk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clk</obj_property>
      <obj_property name="ObjectShortName">clk</obj_property>
   </wvobject>
   <wvobject fp_name="/memdiv_tb/rst" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">rst</obj_property>
      <obj_property name="ObjectShortName">rst</obj_property>
   </wvobject>
   <wvobject fp_name="/memdiv_tb/in_dmem" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">in_dmem</obj_property>
      <obj_property name="ObjectShortName">in_dmem</obj_property>
      <wvobject fp_name="/memdiv_tb/in_dmem.write_data" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.write_data</obj_property>
         <obj_property name="ObjectShortName">in_dmem.write_data</obj_property>
         <obj_property name="Radix">HEXRADIX</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/in_dmem.write_addr" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.write_addr</obj_property>
         <obj_property name="ObjectShortName">in_dmem.write_addr</obj_property>
         <obj_property name="Radix">HEXRADIX</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/in_dmem.write_size" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.write_size</obj_property>
         <obj_property name="ObjectShortName">in_dmem.write_size</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/in_dmem.write_en" type="logic" db_ref_id="1">
         <obj_property name="ElementShortName">.write_en</obj_property>
         <obj_property name="ObjectShortName">in_dmem.write_en</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/in_dmem.read_addr" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.read_addr</obj_property>
         <obj_property name="ObjectShortName">in_dmem.read_addr</obj_property>
         <obj_property name="Radix">HEXRADIX</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/in_dmem.read_size" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.read_size</obj_property>
         <obj_property name="ObjectShortName">in_dmem.read_size</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/in_dmem.read_en" type="logic" db_ref_id="1">
         <obj_property name="ElementShortName">.read_en</obj_property>
         <obj_property name="ObjectShortName">in_dmem.read_en</obj_property>
      </wvobject>
   </wvobject>
   <wvobject fp_name="/memdiv_tb/in_imem" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">in_imem</obj_property>
      <obj_property name="ObjectShortName">in_imem</obj_property>
      <wvobject fp_name="/memdiv_tb/in_imem.read_addr" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.read_addr</obj_property>
         <obj_property name="ObjectShortName">in_imem.read_addr</obj_property>
         <obj_property name="Radix">HEXRADIX</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/in_imem.read_en" type="logic" db_ref_id="1">
         <obj_property name="ElementShortName">.read_en</obj_property>
         <obj_property name="ObjectShortName">in_imem.read_en</obj_property>
      </wvobject>
   </wvobject>
   <wvobject fp_name="/memdiv_tb/out_dmem" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">out_dmem</obj_property>
      <obj_property name="ObjectShortName">out_dmem</obj_property>
      <wvobject fp_name="/memdiv_tb/out_dmem.read_data" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.read_data</obj_property>
         <obj_property name="ObjectShortName">out_dmem.read_data</obj_property>
         <obj_property name="Radix">HEXRADIX</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/out_dmem.ready" type="logic" db_ref_id="1">
         <obj_property name="ElementShortName">.ready</obj_property>
         <obj_property name="ObjectShortName">out_dmem.ready</obj_property>
      </wvobject>
   </wvobject>
   <wvobject fp_name="/memdiv_tb/out_imem" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">out_imem</obj_property>
      <obj_property name="ObjectShortName">out_imem</obj_property>
      <wvobject fp_name="/memdiv_tb/out_imem.read_data" type="array" db_ref_id="1">
         <obj_property name="ElementShortName">.read_data</obj_property>
         <obj_property name="ObjectShortName">out_imem.read_data</obj_property>
         <obj_property name="Radix">HEXRADIX</obj_property>
      </wvobject>
      <wvobject fp_name="/memdiv_tb/out_imem.ready" type="logic" db_ref_id="1">
         <obj_property name="ElementShortName">.ready</obj_property>
         <obj_property name="ObjectShortName">out_imem.ready</obj_property>
      </wvobject>
   </wvobject>
   <wvobject fp_name="/memdiv_tb/fault" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">fault</obj_property>
      <obj_property name="ObjectShortName">fault</obj_property>
   </wvobject>
   <wvobject fp_name="/memdiv_tb/out_byte" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">out_byte[7:0]</obj_property>
      <obj_property name="ObjectShortName">out_byte[7:0]</obj_property>
   </wvobject>
</wave_config>
