-- See the file "LICENSE" for the full license governing this code. --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_global.all;

entity seven_segment_display is
	port(
		clk		: in  std_logic;
		rst		: in  std_logic;
        seg_data : in std_logic_vector(3 downto 0);
        seg_off : in std_logic;
        seg_shift : in std_logic;
        seg_write : in std_logic;
        seg_clear : in std_logic;   
        anodes : out std_logic_vector(7 downto 0);
        cathodes : out std_logic_vector(7 downto 0)
	);
end seven_segment_display;

architecture Behavioral of seven_segment_display is

	signal hex_register : std_logic_vector(63 downto 0);
    signal hex : std_logic_vector(4 downto 0);

    signal timer_overflow : std_logic;
    signal overflow_counter : integer range 0 to 7;

    component hex2physical
    port(
        hex : in std_logic_vector(4 downto 0);
        cathodes : out std_logic_vector(7 downto 0)
    );
    end component;

    component simple_timer
    generic(
        timer_start : std_logic_vector (31 downto 0)
    );
    port(
        clk : in std_logic;
        rst : in std_logic;
        timer_overflow : out std_logic
    );
    end component;

begin

    converter : hex2physical
    port map(
        hex => hex,
        cathodes => cathodes
    );

    timer: simple_timer
    -- generic map (timer_start => x"00000008") -- for simulation
    generic map (timer_start => x"00000F00") -- for board
    port map(
        clk => clk,
        rst => rst,
        timer_overflow => timer_overflow
    );

    process(clk)
    begin
        if clk'event and clk='1' then
			if rst = '1' then
				hex_register <= (others=>'0');
			else                
                -- No special care has to be taken to support
                -- writing and shifting at the same time.
                
                if seg_shift = '1' then
                    hex_register(63 downto 56) <= (others => '0');
                    hex_register(55 downto 0) <= hex_register(63 downto 8);
                end if;
                    
                if seg_write = '1' then
                    hex_register(59 downto 56) <= seg_data;
                    hex_register(60) <= not seg_off; -- unclear if this should only be set when write is 1
                end if;

                if seg_clear = '1' then
                    hex_register <= (others => '0');    
                end if;
            end if;
        end if;
    end process;

    process(clk)
    begin
        if clk'event and clk='1' then
            if rst = '1' then
                hex <= hex_register(4 downto 0);
                anodes <= (others => not '0');
                overflow_counter <= 0;
            else
                if seg_clear = '1' then
                    overflow_counter <= 0;
                elsif timer_overflow = '1' then
                    if overflow_counter = 7 then
                        overflow_counter <= 0;
                    else
                        overflow_counter <= overflow_counter + 1;
                    end if;

                    anodes <= (others => not '0');
                    anodes(overflow_counter) <= not '1';
                    
                    hex <= hex_register(overflow_counter * 8 + 4 downto overflow_counter * 8);
                end if;
            end if;
        end if;
    end process;

end Behavioral;
