a8447b7fc0
The Vega ISA's s_memtime instruction is used to obtain a cycle value from the GPU. Previously, this was implemented to obtain the cycle count when the memtime instruction reached the execute stage of the GPU pipeline. However, from microbenchmarking we have found that this under reports the latency for memtime instructions relative to real hardware. Thus, we changed its behavior to go through the scalar memory pipeline and obtain a latency value from the the SQC (L1 I$). This mirrors the suggestion of the AMD Vega ISA manual that s_memtime should be treated like a s_load_dwordx2. The default latency was set based on microbenchmarking. Change-Id: I5e251dde28c06fe1c492aea4abf9f34f05784420
133 lines
4.9 KiB
Python
133 lines
4.9 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2021,2023 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2009 The Hewlett-Packard Development Company
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import os
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import sys
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from os.path import basename, isdir, join as joinpath
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import SCons
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from gem5_scons import Transform
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Import('*')
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if not env['CONF']['RUBY']:
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Return()
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DebugFlag('ProtocolTrace')
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DebugFlag('RubyCache')
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DebugFlag('RubyCacheTrace')
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DebugFlag('RubyDma')
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DebugFlag('RubyGenerated')
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DebugFlag('RubyNetwork')
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DebugFlag('RubyPort')
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DebugFlag('RubyPrefetcher')
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DebugFlag('RubyQueue')
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DebugFlag('RubySequencer')
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DebugFlag('RubySlicc')
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DebugFlag('RubySystem')
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DebugFlag('RubyTester')
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DebugFlag('RubyStats')
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DebugFlag('RubyResourceStalls')
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DebugFlag('RubyProtocol')
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DebugFlag('RubyHitMiss')
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CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
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'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
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'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
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'RubyPrefetcher', 'RubyProtocol', 'RubyHitMiss'])
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#
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# Link includes
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#
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generated_dir = Dir('protocol')
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def MakeIncludeAction(target, source, env):
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with open(str(target[0]), 'w') as f:
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for s in source:
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print('#include "%s"' % str(s.abspath), file=f)
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def MakeInclude(source):
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target = generated_dir.File(basename(source))
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include_action = MakeAction(MakeIncludeAction, Transform("MAKE INC", 1))
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env.Command(target, source, include_action)
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MakeInclude('slicc_interface/AbstractCacheEntry.hh')
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MakeInclude('slicc_interface/Message.hh')
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MakeInclude('slicc_interface/RubyRequest.hh')
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# External types
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MakeInclude('common/Address.hh')
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MakeInclude('common/BoolVec.hh')
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MakeInclude('common/DataBlock.hh')
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MakeInclude('common/ExpectedMap.hh')
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MakeInclude('common/IntVec.hh')
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MakeInclude('common/MachineID.hh')
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MakeInclude('common/NetDest.hh')
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MakeInclude('common/TriggerQueue.hh')
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MakeInclude('common/Set.hh')
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MakeInclude('common/WriteMask.hh')
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MakeInclude('network/MessageBuffer.hh')
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MakeInclude('structures/CacheMemory.hh')
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MakeInclude('structures/DirectoryMemory.hh')
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MakeInclude('structures/PerfectCacheMemory.hh')
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MakeInclude('structures/PersistentTable.hh')
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MakeInclude('structures/RubyPrefetcher.hh')
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MakeInclude('structures/RubyPrefetcherProxy.hh')
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MakeInclude('structures/TBEStorage.hh')
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if env['CONF']['PROTOCOL'] == 'CHI':
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MakeInclude('structures/MN_TBEStorage.hh')
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MakeInclude('structures/MN_TBETable.hh')
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MakeInclude('structures/TBETable.hh')
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MakeInclude('structures/TimerTable.hh')
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MakeInclude('structures/WireBuffer.hh')
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MakeInclude('system/DMASequencer.hh')
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MakeInclude('system/Sequencer.hh')
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# External types : Group "mem/ruby/protocol" : include "header.hh" to the
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# bottom of this MakeIncludes if it is referenced as
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# <# include "mem/ruby/protocol/header.hh"> in any file
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# generated_dir = Dir('protocol')
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MakeInclude('system/GPUCoalescer.hh')
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MakeInclude('system/HTMSequencer.hh')
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MakeInclude('system/VIPERCoalescer.hh')
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MakeInclude('system/VIPERSequencer.hh')
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