fed81f3408
We add initial support for matrix registers to the CPU models and add stubs in each architecture. There are no implementations of matrix registers added, but this provides the basic support for using them in the future. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289 Change-Id: I2ca6a21da932a58a801a0d08f0ad0cdca4968d02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64333 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
583 lines
20 KiB
C++
583 lines
20 KiB
C++
/*
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* Copyright (c) 2014-2018, 2020-2021 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__
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#define __CPU_SIMPLE_EXEC_CONTEXT_HH__
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#include "base/types.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/reg_class.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/static_inst_fwd.hh"
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#include "cpu/translation.hh"
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#include "mem/request.hh"
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namespace gem5
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{
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class BaseSimpleCPU;
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class SimpleExecContext : public ExecContext
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{
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public:
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BaseSimpleCPU *cpu;
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SimpleThread* thread;
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// This is the offset from the current pc that fetch should be performed
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Addr fetchOffset;
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// This flag says to stay at the current pc. This is useful for
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// instructions which go beyond MachInst boundaries.
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bool stayAtPC;
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// Branch prediction
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std::unique_ptr<PCStateBase> predPC;
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/** PER-THREAD STATS */
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Counter numInst;
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Counter numOp;
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// Number of simulated loads
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Counter numLoad;
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// Number of cycles stalled for I-cache responses
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Counter lastIcacheStall;
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// Number of cycles stalled for D-cache responses
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Counter lastDcacheStall;
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struct ExecContextStats : public statistics::Group
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{
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ExecContextStats(BaseSimpleCPU *cpu, SimpleThread *thread)
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: statistics::Group(cpu,
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csprintf("exec_context.thread_%i",
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thread->threadId()).c_str()),
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ADD_STAT(numInsts, statistics::units::Count::get(),
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"Number of instructions committed"),
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ADD_STAT(numOps, statistics::units::Count::get(),
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"Number of ops (including micro ops) committed"),
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ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
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"Number of integer alu accesses"),
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ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
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"Number of float alu accesses"),
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ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
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"Number of vector alu accesses"),
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ADD_STAT(numMatAluAccesses, statistics::units::Count::get(),
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"Number of matrix alu accesses"),
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ADD_STAT(numCallsReturns, statistics::units::Count::get(),
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"Number of times a function call or return occured"),
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ADD_STAT(numCondCtrlInsts, statistics::units::Count::get(),
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"Number of instructions that are conditional controls"),
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ADD_STAT(numIntInsts, statistics::units::Count::get(),
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"Number of integer instructions"),
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ADD_STAT(numFpInsts, statistics::units::Count::get(),
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"Number of float instructions"),
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ADD_STAT(numVecInsts, statistics::units::Count::get(),
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"Number of vector instructions"),
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ADD_STAT(numMatInsts, statistics::units::Count::get(),
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"Number of matrix instructions"),
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ADD_STAT(numIntRegReads, statistics::units::Count::get(),
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"Number of times the integer registers were read"),
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ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
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"Number of times the integer registers were written"),
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ADD_STAT(numFpRegReads, statistics::units::Count::get(),
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"Number of times the floating registers were read"),
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ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
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"Number of times the floating registers were written"),
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ADD_STAT(numVecRegReads, statistics::units::Count::get(),
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"Number of times the vector registers were read"),
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ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
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"Number of times the vector registers were written"),
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ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
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"Number of times the predicate registers were read"),
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ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
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"Number of times the predicate registers were written"),
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ADD_STAT(numCCRegReads, statistics::units::Count::get(),
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"Number of times the CC registers were read"),
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ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
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"Number of times the CC registers were written"),
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ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
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"Number of times the Misc registers were read"),
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ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
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"Number of times the Misc registers were written"),
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ADD_STAT(numMemRefs, statistics::units::Count::get(),
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"Number of memory refs"),
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ADD_STAT(numLoadInsts, statistics::units::Count::get(),
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"Number of load instructions"),
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ADD_STAT(numStoreInsts, statistics::units::Count::get(),
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"Number of store instructions"),
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ADD_STAT(numIdleCycles, statistics::units::Cycle::get(),
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"Number of idle cycles"),
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ADD_STAT(numBusyCycles, statistics::units::Cycle::get(),
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"Number of busy cycles"),
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ADD_STAT(notIdleFraction, statistics::units::Ratio::get(),
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"Percentage of non-idle cycles"),
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ADD_STAT(idleFraction, statistics::units::Ratio::get(),
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"Percentage of idle cycles"),
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ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
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"ICache total stall cycles"),
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ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
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"DCache total stall cycles"),
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ADD_STAT(numBranches, statistics::units::Count::get(),
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"Number of branches fetched"),
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ADD_STAT(numPredictedBranches, statistics::units::Count::get(),
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"Number of branches predicted as taken"),
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ADD_STAT(numBranchMispred, statistics::units::Count::get(),
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"Number of branch mispredictions"),
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ADD_STAT(statExecutedInstType, statistics::units::Count::get(),
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"Class of executed instruction."),
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numRegReads{
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&numIntRegReads,
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&numFpRegReads,
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&numVecRegReads,
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&numVecRegReads,
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&numVecPredRegReads,
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&numMatRegReads,
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&numCCRegReads
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},
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numRegWrites{
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&numIntRegWrites,
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&numFpRegWrites,
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&numVecRegWrites,
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&numVecRegWrites,
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&numVecPredRegWrites,
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&numMatRegWrites,
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&numCCRegWrites
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}
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{
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numCCRegReads
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.flags(statistics::nozero);
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numCCRegWrites
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.flags(statistics::nozero);
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icacheStallCycles
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.prereq(icacheStallCycles);
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dcacheStallCycles
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.prereq(dcacheStallCycles);
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statExecutedInstType
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.init(enums::Num_OpClass)
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.flags(statistics::total | statistics::pdf | statistics::dist);
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for (unsigned i = 0; i < Num_OpClasses; ++i) {
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statExecutedInstType.subname(i, enums::OpClassStrings[i]);
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}
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idleFraction = statistics::constant(1.0) - notIdleFraction;
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numIdleCycles = idleFraction * cpu->baseStats.numCycles;
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numBusyCycles = notIdleFraction * cpu->baseStats.numCycles;
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numBranches
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.prereq(numBranches);
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numPredictedBranches
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.prereq(numPredictedBranches);
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numBranchMispred
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.prereq(numBranchMispred);
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}
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// Number of simulated instructions
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statistics::Scalar numInsts;
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statistics::Scalar numOps;
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// Number of integer alu accesses
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statistics::Scalar numIntAluAccesses;
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// Number of float alu accesses
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statistics::Scalar numFpAluAccesses;
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// Number of vector alu accesses
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statistics::Scalar numVecAluAccesses;
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// Number of matrix alu accesses
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statistics::Scalar numMatAluAccesses;
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// Number of function calls/returns
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statistics::Scalar numCallsReturns;
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// Conditional control instructions;
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statistics::Scalar numCondCtrlInsts;
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// Number of int instructions
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statistics::Scalar numIntInsts;
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// Number of float instructions
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statistics::Scalar numFpInsts;
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// Number of vector instructions
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statistics::Scalar numVecInsts;
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// Number of matrix instructions
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statistics::Scalar numMatInsts;
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// Number of integer register file accesses
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statistics::Scalar numIntRegReads;
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statistics::Scalar numIntRegWrites;
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// Number of float register file accesses
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statistics::Scalar numFpRegReads;
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statistics::Scalar numFpRegWrites;
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// Number of vector register file accesses
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mutable statistics::Scalar numVecRegReads;
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statistics::Scalar numVecRegWrites;
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// Number of predicate register file accesses
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mutable statistics::Scalar numVecPredRegReads;
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statistics::Scalar numVecPredRegWrites;
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// Number of matrix register file accesses
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mutable statistics::Scalar numMatRegReads;
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statistics::Scalar numMatRegWrites;
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// Number of condition code register file accesses
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statistics::Scalar numCCRegReads;
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statistics::Scalar numCCRegWrites;
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// Number of misc register file accesses
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statistics::Scalar numMiscRegReads;
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statistics::Scalar numMiscRegWrites;
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// Number of simulated memory references
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statistics::Scalar numMemRefs;
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statistics::Scalar numLoadInsts;
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statistics::Scalar numStoreInsts;
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// Number of idle cycles
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statistics::Formula numIdleCycles;
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// Number of busy cycles
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statistics::Formula numBusyCycles;
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// Number of idle cycles
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statistics::Average notIdleFraction;
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statistics::Formula idleFraction;
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// Number of cycles stalled for I-cache responses
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statistics::Scalar icacheStallCycles;
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// Number of cycles stalled for D-cache responses
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statistics::Scalar dcacheStallCycles;
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/// @{
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/// Total number of branches fetched
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statistics::Scalar numBranches;
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/// Number of branches predicted as taken
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statistics::Scalar numPredictedBranches;
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/// Number of misprediced branches
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statistics::Scalar numBranchMispred;
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/// @}
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// Instruction mix histogram by OpClass
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statistics::Vector statExecutedInstType;
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std::array<statistics::Scalar *, CCRegClass + 1> numRegReads;
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std::array<statistics::Scalar *, CCRegClass + 1> numRegWrites;
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} execContextStats;
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public:
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/** Constructor */
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SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread)
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: cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
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numInst(0), numOp(0), numLoad(0), lastIcacheStall(0),
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lastDcacheStall(0), execContextStats(cpu, thread)
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{ }
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RegVal
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getRegOperand(const StaticInst *si, int idx) override
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{
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const RegId ® = si->srcRegIdx(idx);
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if (reg.is(InvalidRegClass))
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return 0;
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(*execContextStats.numRegReads[reg.classValue()])++;
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return thread->getReg(reg);
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}
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void
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getRegOperand(const StaticInst *si, int idx, void *val) override
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{
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const RegId ® = si->srcRegIdx(idx);
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(*execContextStats.numRegReads[reg.classValue()])++;
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thread->getReg(reg, val);
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}
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void *
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getWritableRegOperand(const StaticInst *si, int idx) override
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{
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const RegId ® = si->destRegIdx(idx);
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(*execContextStats.numRegWrites[reg.classValue()])++;
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return thread->getWritableReg(reg);
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}
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void
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setRegOperand(const StaticInst *si, int idx, RegVal val) override
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{
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const RegId ® = si->destRegIdx(idx);
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if (reg.is(InvalidRegClass))
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return;
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(*execContextStats.numRegWrites[reg.classValue()])++;
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thread->setReg(reg, val);
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}
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void
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setRegOperand(const StaticInst *si, int idx, const void *val) override
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{
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const RegId ® = si->destRegIdx(idx);
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(*execContextStats.numRegWrites[reg.classValue()])++;
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thread->setReg(reg, val);
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}
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RegVal
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readMiscRegOperand(const StaticInst *si, int idx) override
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{
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execContextStats.numMiscRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.is(MiscRegClass));
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return thread->readMiscReg(reg.index());
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}
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void
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setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
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{
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execContextStats.numMiscRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.is(MiscRegClass));
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thread->setMiscReg(reg.index(), val);
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}
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/**
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* Reads a miscellaneous register, handling any architectural
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* side effects due to reading that register.
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*/
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RegVal
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readMiscReg(int misc_reg) override
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{
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execContextStats.numMiscRegReads++;
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return thread->readMiscReg(misc_reg);
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}
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/**
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* Sets a miscellaneous register, handling any architectural
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* side effects due to writing that register.
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*/
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void
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setMiscReg(int misc_reg, RegVal val) override
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{
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execContextStats.numMiscRegWrites++;
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thread->setMiscReg(misc_reg, val);
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}
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const PCStateBase &
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pcState() const override
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{
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return thread->pcState();
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}
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void
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pcState(const PCStateBase &val) override
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{
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thread->pcState(val);
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}
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Fault
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readMem(Addr addr, uint8_t *data, unsigned int size,
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Request::Flags flags,
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const std::vector<bool>& byte_enable)
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override
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{
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assert(byte_enable.size() == size);
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return cpu->readMem(addr, data, size, flags, byte_enable);
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}
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Fault
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initiateMemRead(Addr addr, unsigned int size,
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Request::Flags flags,
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const std::vector<bool>& byte_enable)
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override
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{
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assert(byte_enable.size() == size);
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return cpu->initiateMemRead(addr, size, flags, byte_enable);
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}
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Fault
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writeMem(uint8_t *data, unsigned int size, Addr addr,
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Request::Flags flags, uint64_t *res,
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const std::vector<bool>& byte_enable)
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override
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{
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assert(byte_enable.size() == size);
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return cpu->writeMem(data, size, addr, flags, res,
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byte_enable);
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}
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Fault
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amoMem(Addr addr, uint8_t *data, unsigned int size,
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Request::Flags flags, AtomicOpFunctorPtr amo_op) override
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{
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return cpu->amoMem(addr, data, size, flags, std::move(amo_op));
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}
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Fault
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initiateMemAMO(Addr addr, unsigned int size,
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Request::Flags flags,
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AtomicOpFunctorPtr amo_op) override
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{
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return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
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}
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Fault
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initiateMemMgmtCmd(Request::Flags flags) override
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{
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return cpu->initiateMemMgmtCmd(flags);
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}
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/**
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* Sets the number of consecutive store conditional failures.
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*/
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void
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setStCondFailures(unsigned int sc_failures) override
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{
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thread->setStCondFailures(sc_failures);
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}
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/**
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* Returns the number of consecutive store conditional failures.
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*/
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unsigned int
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readStCondFailures() const override
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{
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return thread->readStCondFailures();
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}
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/** Returns a pointer to the ThreadContext. */
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|
ThreadContext *tcBase() const override { return thread->getTC(); }
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bool
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readPredicate() const override
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|
{
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return thread->readPredicate();
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}
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void
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setPredicate(bool val) override
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{
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thread->setPredicate(val);
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if (cpu->traceData) {
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cpu->traceData->setPredicate(val);
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}
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}
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bool
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readMemAccPredicate() const override
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|
{
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return thread->readMemAccPredicate();
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}
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void
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|
setMemAccPredicate(bool val) override
|
|
{
|
|
thread->setMemAccPredicate(val);
|
|
}
|
|
|
|
uint64_t
|
|
getHtmTransactionUid() const override
|
|
{
|
|
return tcBase()->getHtmCheckpointPtr()->getHtmUid();
|
|
}
|
|
|
|
uint64_t
|
|
newHtmTransactionUid() const override
|
|
{
|
|
return tcBase()->getHtmCheckpointPtr()->newHtmUid();
|
|
}
|
|
|
|
bool
|
|
inHtmTransactionalState() const override
|
|
{
|
|
return (getHtmTransactionalDepth() > 0);
|
|
}
|
|
|
|
uint64_t
|
|
getHtmTransactionalDepth() const override
|
|
{
|
|
assert(thread->htmTransactionStarts >= thread->htmTransactionStops);
|
|
return (thread->htmTransactionStarts - thread->htmTransactionStops);
|
|
}
|
|
|
|
/**
|
|
* Invalidate a page in the DTLB <i>and</i> ITLB.
|
|
*/
|
|
void
|
|
demapPage(Addr vaddr, uint64_t asn) override
|
|
{
|
|
thread->demapPage(vaddr, asn);
|
|
}
|
|
|
|
void
|
|
armMonitor(Addr address) override
|
|
{
|
|
cpu->armMonitor(thread->threadId(), address);
|
|
}
|
|
|
|
bool
|
|
mwait(PacketPtr pkt) override
|
|
{
|
|
return cpu->mwait(thread->threadId(), pkt);
|
|
}
|
|
|
|
void
|
|
mwaitAtomic(ThreadContext *tc) override
|
|
{
|
|
cpu->mwaitAtomic(thread->threadId(), tc, thread->mmu);
|
|
}
|
|
|
|
AddressMonitor *
|
|
getAddrMonitor() override
|
|
{
|
|
return cpu->getCpuAddrMonitor(thread->threadId());
|
|
}
|
|
};
|
|
|
|
} // namespace gem5
|
|
|
|
#endif // __CPU_EXEC_CONTEXT_HH__
|