da4f5726be
This generalized Workload SimObject is not geared towards FS or SE simulations, although currently it's only used in FS. This gets rid of the ARM specific highestELIs64 property (from the workload, not the system) and replaces it with a generic getArch. The old globally accessible kernel symtab has been replaced with a symtab accessor which takes a ThreadContext *. The parameter isn't used for anything for now, but in cases where there might be multiple symbol tables to choose from (kernel vs. current user space?) the method will now be able to distinguish which to use. This also makes it possible for the workload to manage its symbol table with whatever policy makes sense for it. That method returns a const SymbolTable * since most of the time the symbol table doesn't need to be modified. In the one case where an external entity needs to modify the table, two pseudo instructions, the table to modify isn't necessarily the one that's currently active. For instance, the pseudo instruction will likely execute in user space, but might be intended to add a symbol to the kernel in case something like a module was loaded. To support that usage, the workload has a generic "insertSymbol" method which will insert the symbol in the table that "makes sense". There is a lot of ambiguity what that means, but it's no less ambiguous than today where we're only saved by the fact that there is generally only one active symbol table to worry about. This change also introduces a KernelWorkload SimObject class which inherits from Workload and adds in kernel related members for cases where the kernel is specified in the config and loaded by gem5 itself. That's the common case, but the base Workload class would be used directly when, for instance, doing a baremetal simulation or if the kernel is loaded by software within the simulation as is the case for SPARC FS. Because a given architecture specific workload class needs to inherit from either Workload or KernelWorkload, this change removes the ability to boot ARM without a kernel. This ability should be restored in the future. To make having or not having a kernel more flexible, the kernel specific members of the KernelWorkload should be factored out into their own object which can then be attached to a workload through a (potentially unused) property rather than inheritance. Change-Id: Idf72615260266d7b4478d20d4035ed5a1e7aa241 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24283 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
123 lines
5.7 KiB
Python
123 lines
5.7 KiB
Python
# Copyright (c) 2017, 2019 ARM Limited
|
|
# All rights reserved.
|
|
#
|
|
# The license below extends only to copyright in the software and shall
|
|
# not be construed as granting a license to any other intellectual
|
|
# property including but not limited to intellectual property relating
|
|
# to a hardware implementation of the functionality of the software
|
|
# licensed hereunder. You may use the software subject to the license
|
|
# terms below provided that you ensure that this notice is replicated
|
|
# unmodified and in its entirety in all distributions of the software,
|
|
# modified or unmodified, in source code or in binary form.
|
|
#
|
|
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
|
# Copyright (c) 2011 Regents of the University of California
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
from m5.SimObject import *
|
|
from m5.defines import buildEnv
|
|
from m5.params import *
|
|
from m5.proxy import *
|
|
|
|
from m5.objects.DVFSHandler import *
|
|
from m5.objects.SimpleMemory import *
|
|
|
|
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
|
|
'atomic_noncaching']
|
|
|
|
class System(SimObject):
|
|
type = 'System'
|
|
cxx_header = "sim/system.hh"
|
|
system_port = MasterPort("System port")
|
|
|
|
cxx_exports = [
|
|
PyBindMethod("getMemoryMode"),
|
|
PyBindMethod("setMemoryMode"),
|
|
]
|
|
|
|
memories = VectorParam.AbstractMemory(Self.all,
|
|
"All memories in the system")
|
|
mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
|
|
|
|
thermal_model = Param.ThermalModel(NULL, "Thermal model")
|
|
thermal_components = VectorParam.SimObject([],
|
|
"A collection of all thermal components in the system.")
|
|
|
|
# When reserving memory on the host, we have the option of
|
|
# reserving swap space or not (by passing MAP_NORESERVE to
|
|
# mmap). By enabling this flag, we accommodate cases where a large
|
|
# (but sparse) memory is simulated.
|
|
mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \
|
|
"without reserving swap")
|
|
|
|
# The memory ranges are to be populated when creating the system
|
|
# such that these can be passed from the I/O subsystem through an
|
|
# I/O bridge or cache
|
|
mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
|
|
|
|
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
|
|
|
|
redirect_paths = VectorParam.RedirectPath([], "Path redirections")
|
|
|
|
exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "
|
|
"encountering work item annotations.")
|
|
work_item_id = Param.Int(-1, "specific work item id")
|
|
num_work_ids = Param.Int(16, "Number of distinct work item types")
|
|
work_begin_cpu_id_exit = Param.Int(-1,
|
|
"work started on specific id, now exit simulation")
|
|
work_begin_ckpt_count = Param.Counter(0,
|
|
"create checkpoint when work items begin count value is reached")
|
|
work_begin_exit_count = Param.Counter(0,
|
|
"exit simulation when work items begin count value is reached")
|
|
work_end_ckpt_count = Param.Counter(0,
|
|
"create checkpoint when work items end count value is reached")
|
|
work_end_exit_count = Param.Counter(0,
|
|
"exit simulation when work items end count value is reached")
|
|
work_cpus_ckpt_count = Param.Counter(0,
|
|
"create checkpoint when active cpu count value is reached")
|
|
|
|
workload = Param.Workload(NULL, "Operating system kernel")
|
|
init_param = Param.UInt64(0, "numerical value to pass into simulator")
|
|
readfile = Param.String("", "file to read startup script from")
|
|
symbolfile = Param.String("", "file to get the symbols from")
|
|
|
|
multi_thread = Param.Bool(False,
|
|
"Supports multi-threaded CPUs? Impacts Thread/Context IDs")
|
|
|
|
# Dynamic voltage and frequency handler for the system, disabled by default
|
|
# Provide list of domains that need to be controlled by the handler
|
|
dvfs_handler = DVFSHandler()
|
|
|
|
# SE mode doesn't use the ISA System subclasses, and so we need to set an
|
|
# ISA specific value in this class directly.
|
|
m5ops_base = Param.Addr(
|
|
0xffff0000 if buildEnv['TARGET_ISA'] == 'x86' else 0,
|
|
"Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
|
|
"to disable.")
|
|
|
|
if buildEnv['USE_KVM']:
|
|
kvm_vm = Param.KvmVM(NULL, 'KVM VM (i.e., shared memory domain)')
|