src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
144 lines
5.2 KiB
C++
144 lines
5.2 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Steve Reinhardt
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*/
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/**
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* @file
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* Definition of the Packet Class, a packet is a transaction occuring
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* between a single level of the memory heirarchy (ie L1->L2).
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*/
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#include "base/misc.hh"
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#include "mem/packet.hh"
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static const std::string ReadReqString("ReadReq");
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static const std::string WriteReqString("WriteReq");
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static const std::string WriteReqNoAckString("WriteReqNoAck|Writeback");
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static const std::string ReadRespString("ReadResp");
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static const std::string WriteRespString("WriteResp");
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static const std::string SoftPFReqString("SoftPFReq");
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static const std::string SoftPFRespString("SoftPFResp");
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static const std::string HardPFReqString("HardPFReq");
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static const std::string HardPFRespString("HardPFResp");
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static const std::string InvalidateReqString("InvalidateReq");
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static const std::string WriteInvalidateReqString("WriteInvalidateReq");
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static const std::string UpgradeReqString("UpgradeReq");
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static const std::string ReadExReqString("ReadExReq");
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static const std::string ReadExRespString("ReadExResp");
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static const std::string OtherCmdString("<other>");
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const std::string &
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Packet::cmdString() const
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{
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switch (cmd) {
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case ReadReq: return ReadReqString;
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case WriteReq: return WriteReqString;
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case WriteReqNoAck: return WriteReqNoAckString;
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case ReadResp: return ReadRespString;
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case WriteResp: return WriteRespString;
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case SoftPFReq: return SoftPFReqString;
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case SoftPFResp: return SoftPFRespString;
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case HardPFReq: return HardPFReqString;
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case HardPFResp: return HardPFRespString;
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case InvalidateReq: return InvalidateReqString;
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case WriteInvalidateReq:return WriteInvalidateReqString;
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case UpgradeReq: return UpgradeReqString;
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case ReadExReq: return ReadExReqString;
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case ReadExResp: return ReadExRespString;
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default: return OtherCmdString;
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}
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}
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const std::string &
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Packet::cmdIdxToString(Packet::Command idx)
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{
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switch (idx) {
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case ReadReq: return ReadReqString;
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case WriteReq: return WriteReqString;
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case WriteReqNoAck: return WriteReqNoAckString;
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case ReadResp: return ReadRespString;
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case WriteResp: return WriteRespString;
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case SoftPFReq: return SoftPFReqString;
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case SoftPFResp: return SoftPFRespString;
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case HardPFReq: return HardPFReqString;
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case HardPFResp: return HardPFRespString;
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case InvalidateReq: return InvalidateReqString;
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case WriteInvalidateReq:return WriteInvalidateReqString;
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case UpgradeReq: return UpgradeReqString;
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case ReadExReq: return ReadExReqString;
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case ReadExResp: return ReadExRespString;
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default: return OtherCmdString;
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}
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}
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/** delete the data pointed to in the data pointer. Ok to call to matter how
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* data was allocted. */
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void
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Packet::deleteData()
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{
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assert(staticData || dynamicData);
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if (staticData)
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return;
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if (arrayData)
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delete [] data;
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else
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delete data;
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}
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/** If there isn't data in the packet, allocate some. */
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void
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Packet::allocate()
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{
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if (data)
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return;
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assert(!staticData);
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dynamicData = true;
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arrayData = true;
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data = new uint8_t[getSize()];
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}
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/** Do the packet modify the same addresses. */
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bool
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Packet::intersect(Packet *p)
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{
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Addr s1 = getAddr();
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Addr e1 = getAddr() + getSize() - 1;
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Addr s2 = p->getAddr();
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Addr e2 = p->getAddr() + p->getSize() - 1;
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return !(s1 > e2 || e1 < s2);
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}
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bool
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fixPacket(Packet *func, Packet *timing)
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{
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panic("Need to implement!");
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}
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