Ron Dreslinski fe230ddb8f Remove bus and top level parameters from cache ...

src/mem/cache/base_cache.hh:
    Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
    Remove top level parameters from the cache

--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0

2006-10-12 14:21:25 -04:00

..

coherence

Remove bus and top level parameters from cache

2006-10-12 14:21:25 -04:00

miss

Fix problems with unCacheable addresses in timing-coherence

2006-10-12 13:33:21 -04:00

prefetch

Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.

2006-08-15 16:21:46 -04:00

tags

Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.

2006-08-15 16:21:46 -04:00

base_cache.cc

Check the response queue on functional accesses.

2006-10-12 13:59:03 -04:00

base_cache.hh

Remove bus and top level parameters from cache

2006-10-12 14:21:25 -04:00

cache_blk.hh

#include of iostream needed.

2006-08-11 20:23:31 -04:00

cache_builder.cc

Fix the packet data allocation methods. Small fixes from changesets after my initial work.

2006-06-30 11:34:27 -04:00

cache_impl.hh

Remove bus and top level parameters from cache

2006-10-12 14:21:25 -04:00

cache.cc

Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon.

2006-06-28 11:02:14 -04:00

cache.hh

Fix several bugs pertaining to upgrades/mem leaks.

2006-10-10 01:32:18 -04:00