190c47270e
The way these were set up, there would be a conflict between SimObject files with the same name set up for different ISAs. This change creates a single file which tries to determine how many ISAs are enabled, and if there is exactly one, it creates a backwards compatible alias for the ISA specific CPU types. Change-Id: Iab358c2880d49222e814a98354c81d0f306fe1fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52493 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
77 lines
3.3 KiB
Python
77 lines
3.3 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2013-2014 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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if not env['CONF']['USE_NULL_ISA']:
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SimObject('BaseMinorCPU.py', sim_objects=[
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'MinorOpClass', 'MinorOpClassSet', 'MinorFUTiming', 'MinorFU',
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'MinorFUPool', 'BaseMinorCPU'],
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enums=['ThreadPolicy'])
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Source('activity.cc')
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Source('cpu.cc')
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Source('decode.cc')
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Source('dyn_inst.cc')
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Source('execute.cc')
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Source('fetch1.cc')
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Source('fetch2.cc')
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Source('func_unit.cc')
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Source('lsq.cc')
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Source('pipe_data.cc')
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Source('pipeline.cc')
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Source('scoreboard.cc')
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Source('stats.cc')
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DebugFlag('MinorCPU', 'Minor CPU-level events')
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DebugFlag('MinorExecute', 'Minor Execute stage')
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DebugFlag('MinorInterrupt', 'Minor interrupt handling')
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DebugFlag('MinorMem', 'Minor memory accesses')
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DebugFlag('MinorScoreboard', 'Minor Execute register scoreboard')
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DebugFlag('MinorTrace', 'MinorTrace cycle-by-cycle state trace')
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DebugFlag('MinorTiming', 'Extra timing for instructions')
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CompoundFlag('Minor', [
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'MinorCPU', 'MinorExecute', 'MinorInterrupt', 'MinorMem',
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'MinorScoreboard'])
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# For backwards compatibility
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SimObject('MinorCPU.py', sim_objects=[])
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