fc4caa6ad0
These were universally removed a while ago, but a bunch have crept back in. Remove them. Change-Id: I3cb5b9f40c9c19aafb5e39a51d1baeae60a591c0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40335 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Gabe Black <gabe.black@gmail.com>
104 lines
3.3 KiB
C++
104 lines
3.3 KiB
C++
/*
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* Copyright (c) 2016-2018 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_GCN3_GPU_ISA_HH__
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#define __ARCH_GCN3_GPU_ISA_HH__
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#include <array>
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#include <type_traits>
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#include "arch/gcn3/registers.hh"
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#include "gpu-compute/dispatcher.hh"
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#include "gpu-compute/hsa_queue_entry.hh"
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#include "gpu-compute/misc.hh"
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class Wavefront;
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namespace Gcn3ISA
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{
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class GPUISA
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{
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public:
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GPUISA(Wavefront &wf);
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template<typename T> T
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readConstVal(int opIdx) const
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{
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panic_if(!std::is_integral<T>::value, "Constant values must "
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"be an integer.\n");
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T val(0);
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if (isPosConstVal(opIdx)) {
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val = (T)readPosConstReg(opIdx);
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}
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if (isNegConstVal(opIdx)) {
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val = (T)readNegConstReg(opIdx);
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}
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return val;
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}
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ScalarRegU32 readMiscReg(int opIdx) const;
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void writeMiscReg(int opIdx, ScalarRegU32 operandVal);
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bool hasScalarUnit() const { return true; }
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void advancePC(GPUDynInstPtr gpuDynInst);
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private:
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ScalarRegU32 readPosConstReg(int opIdx) const
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{
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return posConstRegs[opIdx - REG_INT_CONST_POS_MIN];
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}
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ScalarRegI32 readNegConstReg(int opIdx) const
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{
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return negConstRegs[opIdx - REG_INT_CONST_NEG_MIN];
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}
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static const std::array<const ScalarRegU32, NumPosConstRegs>
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posConstRegs;
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static const std::array<const ScalarRegI32, NumNegConstRegs>
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negConstRegs;
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// parent wavefront
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Wavefront &wavefront;
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// shader status bits
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StatusReg statusReg;
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// memory descriptor reg
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ScalarRegU32 m0;
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};
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} // namespace Gcn3ISA
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#endif // __ARCH_GCN3_GPU_ISA_HH__
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