85c1fdac29
The baremetal platform is the platform we use for running user supplied binaries on baremetal hardware. (simply put, it runs provided binaries without adding a gem5 bootloader) Some layers of this software stack might not have a pci driver. This might be the case for firmware images like edkII which needs to use a block device to extract the bootloader and/or the kernel image. Those can use the memory mapped (in host domain) virtio block device which is already part of the VExpress_GEM5 platforms Change-Id: I9c6ba7e1b4566a3999fd9ba20a2bebe191dc3ef8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39995 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
262 lines
10 KiB
Python
262 lines
10 KiB
Python
# Copyright (c) 2016-2017,2019-2021 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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"""This script is the full system example script from the ARM
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Research Starter Kit on System Modeling. More information can be found
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at: http://www.arm.com/ResearchEnablement/SystemModeling
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"""
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import os
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import m5
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from m5.util import addToPath
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from m5.objects import *
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from m5.options import *
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import argparse
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m5.util.addToPath('../..')
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from common import SysPaths
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from common import MemConfig
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from common import ObjectList
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from common.cores.arm import HPI
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import devices
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import workloads
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# Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
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# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
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# the cache class may be 'None' if the particular cache is not present.
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cpu_types = {
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"atomic" : ( AtomicSimpleCPU, None, None, None, None),
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"minor" : (MinorCPU,
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devices.L1I, devices.L1D,
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devices.WalkCache,
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devices.L2),
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"hpi" : ( HPI.HPI,
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HPI.HPI_ICache, HPI.HPI_DCache,
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HPI.HPI_WalkCache,
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HPI.HPI_L2)
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}
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def create_cow_image(name):
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"""Helper function to create a Copy-on-Write disk image"""
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image = CowDiskImage()
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image.child.image_file = name
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return image;
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def create(args):
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''' Create and configure the system object. '''
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if args.readfile and not os.path.isfile(args.readfile):
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print("Error: Bootscript %s does not exist" % args.readfile)
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sys.exit(1)
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object_file = args.kernel if args.kernel else ""
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cpu_class = cpu_types[args.cpu][0]
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mem_mode = cpu_class.memory_mode()
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# Only simulate caches when using a timing CPU (e.g., the HPI model)
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want_caches = True if mem_mode == "timing" else False
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platform = ObjectList.platform_list.get(args.machine_type)
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system = devices.simpleSystem(ArmSystem,
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want_caches,
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args.mem_size,
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platform=platform(),
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mem_mode=mem_mode,
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readfile=args.readfile)
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MemConfig.config_mem(args, system)
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if args.semi_enable:
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system.semihosting = ArmSemihosting(
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stdin=args.semi_stdin,
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stdout=args.semi_stdout,
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stderr=args.semi_stderr,
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files_root_dir=args.semi_path,
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cmd_line = " ".join([ object_file ] + args.args)
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)
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if args.disk_image:
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# Create a VirtIO block device for the system's boot
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# disk. Attach the disk image using gem5's Copy-on-Write
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# functionality to avoid writing changes to the stored copy of
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# the disk image.
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system.realview.vio[0].vio = VirtIOBlock(
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image=create_cow_image(args.disk_image))
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# Wire up the system's memory system
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system.connect()
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# Add CPU clusters to the system
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system.cpu_cluster = [
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devices.CpuCluster(system,
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args.num_cores,
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args.cpu_freq, "1.0V",
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*cpu_types[args.cpu]),
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]
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# Create a cache hierarchy for the cluster. We are assuming that
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# clusters have core-private L1 caches and an L2 that's shared
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# within the cluster.
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for cluster in system.cpu_cluster:
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system.addCaches(want_caches, last_cache_level=2)
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# Setup gem5's minimal Linux boot loader.
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system.auto_reset_addr = True
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# Using GICv3
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system.realview.gic.gicv4 = False
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system.highest_el_is_64 = True
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system.have_virtualization = True
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system.have_security = True
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workload_class = workloads.workload_list.get(args.workload)
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system.workload = workload_class(
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object_file, system)
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return system
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def run(args):
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cptdir = m5.options.outdir
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if args.checkpoint:
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print("Checkpoint directory: %s" % cptdir)
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while True:
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event = m5.simulate()
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exit_msg = event.getCause()
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if exit_msg == "checkpoint":
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print("Dropping checkpoint at tick %d" % m5.curTick())
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cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick())
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m5.checkpoint(os.path.join(cpt_dir))
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print("Checkpoint done.")
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else:
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print(exit_msg, " @ ", m5.curTick())
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break
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sys.exit(event.getCode())
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def main():
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parser = argparse.ArgumentParser(epilog=__doc__)
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parser.add_argument("--kernel", type=str,
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default=None,
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help="Binary to run")
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parser.add_argument("--workload", type=str,
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default="ArmBaremetal",
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choices=workloads.workload_list.get_names(),
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help="Workload type")
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parser.add_argument("--disk-image", type=str,
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default=None,
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help="Disk to instantiate")
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parser.add_argument("--readfile", type=str, default="",
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help = "File to return with the m5 readfile command")
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parser.add_argument("--cpu", type=str, choices=list(cpu_types.keys()),
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default="atomic",
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help="CPU model to use")
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parser.add_argument("--cpu-freq", type=str, default="4GHz")
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parser.add_argument("--num-cores", type=int, default=1,
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help="Number of CPU cores")
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parser.add_argument("--machine-type", type=str,
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choices=ObjectList.platform_list.get_names(),
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default="VExpress_GEM5_V2",
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help="Hardware platform class")
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parser.add_argument("--mem-type", default="DDR3_1600_8x8",
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choices=ObjectList.mem_list.get_names(),
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help = "type of memory to use")
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parser.add_argument("--mem-channels", type=int, default=1,
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help = "number of memory channels")
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parser.add_argument("--mem-ranks", type=int, default=None,
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help = "number of memory ranks per channel")
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parser.add_argument("--mem-size", action="store", type=str,
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default="2GB",
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help="Specify the physical memory size")
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parser.add_argument("--checkpoint", action="store_true")
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parser.add_argument("--restore", type=str, default=None)
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parser.add_argument("--dtb-gen", action="store_true",
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help="Doesn't run simulation, it generates a DTB only")
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parser.add_argument("--semi-enable", action="store_true",
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help="Enable semihosting support")
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parser.add_argument("--semi-stdin", type=str, default="stdin",
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help="Standard input for semihosting " \
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"(default: gem5's stdin)")
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parser.add_argument("--semi-stdout", type=str, default="stdout",
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help="Standard output for semihosting " \
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"(default: gem5's stdout)")
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parser.add_argument("--semi-stderr", type=str, default="stderr",
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help="Standard error for semihosting " \
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"(default: gem5's stderr)")
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parser.add_argument('--semi-path', type=str,
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default="",
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help=('Search path for files to be loaded through '
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'Arm Semihosting'))
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parser.add_argument("args", default=[], nargs="*",
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help="Semihosting arguments to pass to benchmark")
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parser.add_argument("-P", "--param", action="append", default=[],
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help="Set a SimObject parameter relative to the root node. "
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"An extended Python multi range slicing syntax can be used "
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"for arrays. For example: "
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"'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
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"sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
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"Direct parameters of the root object are not accessible, "
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"only parameters of its children.")
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args = parser.parse_args()
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root = Root(full_system=True)
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root.system = create(args)
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root.apply_config(args.param)
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if args.restore is not None:
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m5.instantiate(args.restore)
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else:
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m5.instantiate()
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if args.dtb_gen:
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# No run, autogenerate DTB and exit
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root.system.generateDtb(os.path.join(m5.options.outdir, 'system.dtb'))
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else:
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run(args)
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if __name__ == "__m5_main__":
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main()
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