d25b722e4a
This patch removes the data block present in the directory entry structure of each protocol in gem5's mainline. Firstly, this is required for moving towards common set of memory controllers for classic and ruby memory systems. Secondly, the data block was being misused in several places. It was being used for having free access to the physical memory instead of calling on the memory controller. From now on, the directory controller will not have a direct visibility into the physical memory. The Memory Vector object now resides in the Memory Controller class. This also means that some significant changes are being made to the functional accesses in ruby.
520 lines
15 KiB
Plaintext
520 lines
15 KiB
Plaintext
/*
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* Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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machine(L1Cache, "MI Example L1 Cache")
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: Sequencer * sequencer;
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CacheMemory * cacheMemory;
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Cycles cache_response_latency := 12;
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Cycles issue_latency := 2;
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bool send_evictions;
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// NETWORK BUFFERS
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MessageBuffer * requestFromCache, network="To", virtual_network="2",
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ordered="true", vnet_type="request";
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MessageBuffer * responseFromCache, network="To", virtual_network="4",
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ordered="true", vnet_type="response";
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MessageBuffer * forwardToCache, network="From", virtual_network="3",
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ordered="true", vnet_type="forward";
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MessageBuffer * responseToCache, network="From", virtual_network="4",
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ordered="true", vnet_type="response";
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{
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// STATES
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state_declaration(State, desc="Cache states") {
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I, AccessPermission:Invalid, desc="Not Present/Invalid";
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II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
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M, AccessPermission:Read_Write, desc="Modified";
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MI, AccessPermission:Busy, desc="Modified, issued PUT";
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MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
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IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
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IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
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}
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// EVENTS
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enumeration(Event, desc="Cache events") {
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// From processor
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Load, desc="Load request from processor";
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Ifetch, desc="Ifetch request from processor";
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Store, desc="Store request from processor";
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Data, desc="Data from network";
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Fwd_GETX, desc="Forward from network";
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Inv, desc="Invalidate request from dir";
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Replacement, desc="Replace a block";
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Writeback_Ack, desc="Ack from the directory for a writeback";
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Writeback_Nack, desc="Nack from the directory for a writeback";
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}
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// STRUCTURE DEFINITIONS
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MessageBuffer mandatoryQueue, ordered="false";
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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DataBlock DataBlk, desc="Data in the block";
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}
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// TBE fields
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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// STRUCTURES
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TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
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// PROTOTYPES
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void set_cache_entry(AbstractCacheEntry a);
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void unset_cache_entry();
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void set_tbe(TBE b);
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void unset_tbe();
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void profileMsgDelay(int virtualNetworkType, Cycles b);
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Entry getCacheEntry(Address address), return_by_pointer="yes" {
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return static_cast(Entry, "pointer", cacheMemory.lookup(address));
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}
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// FUNCTIONS
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Event mandatory_request_type_to_event(RubyRequestType type) {
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if (type == RubyRequestType:LD) {
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return Event:Load;
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} else if (type == RubyRequestType:IFETCH) {
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return Event:Ifetch;
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} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
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return Event:Store;
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} else {
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error("Invalid RubyRequestType");
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}
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}
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State getState(TBE tbe, Entry cache_entry, Address addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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}
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else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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else {
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return State:I;
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}
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}
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void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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AccessPermission getAccessPermission(Address addr) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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return L1Cache_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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return L1Cache_State_to_permission(cache_entry.CacheState);
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}
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Entry cache_entry, Address addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(L1Cache_State_to_permission(state));
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}
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}
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void functionalRead(Address addr, Packet *pkt) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
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}
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}
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int functionalWrite(Address addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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return num_functional_writes;
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}
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
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return num_functional_writes;
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}
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// NETWORK PORTS
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out_port(requestNetwork_out, RequestMsg, requestFromCache);
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out_port(responseNetwork_out, ResponseMsg, responseFromCache);
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in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
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if (forwardRequestNetwork_in.isReady()) {
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peek(forwardRequestNetwork_in, RequestMsg, block_on="Addr") {
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Entry cache_entry := getCacheEntry(in_msg.Addr);
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TBE tbe := TBEs[in_msg.Addr];
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if (in_msg.Type == CoherenceRequestType:GETX) {
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trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
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}
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else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
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trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe);
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}
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else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
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trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe);
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}
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else if (in_msg.Type == CoherenceRequestType:INV) {
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trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
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}
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else {
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error("Unexpected message");
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}
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}
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}
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}
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in_port(responseNetwork_in, ResponseMsg, responseToCache) {
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if (responseNetwork_in.isReady()) {
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peek(responseNetwork_in, ResponseMsg, block_on="Addr") {
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Entry cache_entry := getCacheEntry(in_msg.Addr);
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TBE tbe := TBEs[in_msg.Addr];
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if (in_msg.Type == CoherenceResponseType:DATA) {
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trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
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}
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else {
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error("Unexpected message");
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}
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}
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}
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}
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// Mandatory Queue
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in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady()) {
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peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
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Entry cache_entry := getCacheEntry(in_msg.LineAddress);
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if (is_invalid(cache_entry) &&
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cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
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// make room for the block
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trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress),
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getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
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TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
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}
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else {
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
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cache_entry, TBEs[in_msg.LineAddress]);
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}
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}
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}
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}
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// ACTIONS
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action(a_issueRequest, "a", desc="Issue a request") {
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enqueue(requestNetwork_out, RequestMsg, issue_latency) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceRequestType:GETX;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Control;
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}
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}
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action(b_issuePUT, "b", desc="Issue a PUT request") {
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enqueue(requestNetwork_out, RequestMsg, issue_latency) {
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assert(is_valid(cache_entry));
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out_msg.Addr := address;
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out_msg.Type := CoherenceRequestType:PUTX;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.MessageSize := MessageSizeType:Data;
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}
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}
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action(e_sendData, "e", desc="Send data from cache to requestor") {
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peek(forwardRequestNetwork_in, RequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
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assert(is_valid(cache_entry));
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out_msg.Addr := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
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peek(forwardRequestNetwork_in, RequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, cache_response_latency) {
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assert(is_valid(tbe));
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out_msg.Addr := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.DataBlk := tbe.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
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if (is_valid(cache_entry)) {
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} else {
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set_cache_entry(cacheMemory.allocate(address, new Entry));
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}
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}
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action(h_deallocateL1CacheBlock, "h", desc="deallocate a cache block") {
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if (is_valid(cache_entry)) {
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cacheMemory.deallocate(address);
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unset_cache_entry();
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}
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}
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action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
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mandatoryQueue_in.dequeue();
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}
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action(n_popResponseQueue, "n", desc="Pop the response queue") {
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profileMsgDelay(1, responseNetwork_in.dequeue());
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}
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action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") {
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profileMsgDelay(2, forwardRequestNetwork_in.dequeue());
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}
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action(p_profileMiss, "pi", desc="Profile cache miss") {
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++cacheMemory.demand_misses;
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}
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action(p_profileHit, "ph", desc="Profile cache miss") {
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++cacheMemory.demand_hits;
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}
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action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
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assert(is_valid(cache_entry));
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DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
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sequencer.readCallback(address, cache_entry.DataBlk, false);
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}
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action(rx_load_hit, "rx", desc="External load completed.") {
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peek(responseNetwork_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
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sequencer.readCallback(address, cache_entry.DataBlk, true,
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machineIDToMachineType(in_msg.Sender));
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}
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}
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action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
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assert(is_valid(cache_entry));
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DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
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sequencer.writeCallback(address, cache_entry.DataBlk, false);
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}
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action(sx_store_hit, "sx", desc="External store completed.") {
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peek(responseNetwork_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
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sequencer.writeCallback(address, cache_entry.DataBlk, true,
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machineIDToMachineType(in_msg.Sender));
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}
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}
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action(u_writeDataToCache, "u", desc="Write data to the cache") {
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peek(responseNetwork_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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cache_entry.DataBlk := in_msg.DataBlk;
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}
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}
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action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
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if (send_evictions) {
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DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
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sequencer.evictionCallback(address);
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}
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}
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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}
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action(w_deallocateTBE, "w", desc="Deallocate TBE") {
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TBEs.deallocate(address);
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unset_tbe();
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}
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action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
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assert(is_valid(cache_entry));
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assert(is_valid(tbe));
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tbe.DataBlk := cache_entry.DataBlk;
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}
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action(z_stall, "z", desc="stall") {
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// do nothing
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}
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// TRANSITIONS
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transition({IS, IM, MI, II, MII}, {Load, Ifetch, Store, Replacement}) {
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z_stall;
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}
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transition({IS, IM}, {Fwd_GETX, Inv}) {
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z_stall;
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}
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transition(MI, Inv) {
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o_popForwardedRequestQueue;
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}
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transition(M, Store) {
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s_store_hit;
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p_profileHit;
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m_popMandatoryQueue;
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}
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transition(M, {Load, Ifetch}) {
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r_load_hit;
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p_profileHit;
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m_popMandatoryQueue;
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}
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transition(I, Inv) {
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o_popForwardedRequestQueue;
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}
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transition(I, Store, IM) {
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v_allocateTBE;
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i_allocateL1CacheBlock;
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a_issueRequest;
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p_profileMiss;
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m_popMandatoryQueue;
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}
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transition(I, {Load, Ifetch}, IS) {
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v_allocateTBE;
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i_allocateL1CacheBlock;
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a_issueRequest;
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p_profileMiss;
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m_popMandatoryQueue;
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}
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transition(IS, Data, M) {
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u_writeDataToCache;
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rx_load_hit;
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w_deallocateTBE;
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n_popResponseQueue;
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}
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transition(IM, Data, M) {
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u_writeDataToCache;
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sx_store_hit;
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w_deallocateTBE;
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n_popResponseQueue;
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}
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transition(M, Fwd_GETX, I) {
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e_sendData;
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forward_eviction_to_cpu;
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o_popForwardedRequestQueue;
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}
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transition(I, Replacement) {
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h_deallocateL1CacheBlock;
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}
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transition(M, {Replacement,Inv}, MI) {
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v_allocateTBE;
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b_issuePUT;
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x_copyDataFromCacheToTBE;
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forward_eviction_to_cpu;
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h_deallocateL1CacheBlock;
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}
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transition(MI, Writeback_Ack, I) {
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w_deallocateTBE;
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o_popForwardedRequestQueue;
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}
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transition(MI, Fwd_GETX, II) {
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ee_sendDataFromTBE;
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o_popForwardedRequestQueue;
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}
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transition(MI, Writeback_Nack, MII) {
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o_popForwardedRequestQueue;
|
|
}
|
|
|
|
transition(MII, Fwd_GETX, I) {
|
|
ee_sendDataFromTBE;
|
|
w_deallocateTBE;
|
|
o_popForwardedRequestQueue;
|
|
}
|
|
|
|
transition(II, Writeback_Nack, I) {
|
|
w_deallocateTBE;
|
|
o_popForwardedRequestQueue;
|
|
}
|
|
}
|