Andreas Hansson fc315901ff mem: Unify all cache DPRINTF address formatting ...

This patch changes all the DPRINTF messages in the cache to use
'%#llx' every time a packet address is printed. The inclusion of '#'
ensures '0x' is prepended, and since the address type is a uint64_t %x
really should be %llx.

2015-03-02 04:00:56 -05:00

..

prefetch

mem: Change prefetcher to use random_mt

2014-12-23 09:31:19 -05:00

tags

mem: Clarify usage of latency in the cache

2015-02-11 10:23:36 -05:00

base.cc

mem: Tidy up the cache debug messages

2015-03-02 04:00:37 -05:00

base.hh

mem: Tidy up the cache debug messages

2015-03-02 04:00:37 -05:00

BaseCache.py

mem: Add parameter to reserve MSHR entries for demand access

2014-12-23 09:31:18 -05:00

blk.cc

mem: Add support for a security bit in the memory system

2014-01-24 15:29:30 -06:00

blk.hh

mem: Remove WriteInvalidate support

2014-12-02 06:08:17 -05:00

cache_impl.hh

mem: Unify all cache DPRINTF address formatting

2015-03-02 04:00:56 -05:00

cache.cc

mem: refactor LRU cache tags and add random replacement tags

2014-07-28 12:23:23 -04:00

cache.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

mshr_queue.cc

mem: Clarify cache behaviour for pending dirty responses

2015-02-03 14:25:59 -05:00

mshr_queue.hh

mem: Clarify cache behaviour for pending dirty responses

2015-02-03 14:25:59 -05:00

mshr.cc

mem: Unify all cache DPRINTF address formatting

2015-03-02 04:00:56 -05:00

mshr.hh

mem: Clarify cache behaviour for pending dirty responses

2015-02-03 14:25:59 -05:00

SConscript

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00