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Giacomo Travaglini 847f642f0e arch-arm: Add TxSZ to PageTableOps::index 
This patch is adding the input address (IA) size (TSZ) to the
index method, as it is limiting the number of bits used to
determine the descriptor index from the input address

Change-Id: Ibc8f9ce94ea0ce06093bd90546ca1a906518b700
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51807
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-21 08:06:44 +00:00
..
amdgpu
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
arm
arch-arm: Add TxSZ to PageTableOps::index
2021-10-21 08:06:44 +00:00
hsa
dev-hsa,gpu-compute: fix bug with gfx8 VAs for HSA Queues
2021-10-12 17:01:52 +00:00
i2c
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mips
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
net
misc: Replace THE_ISA macro with IS_NULL_ISA.
2021-08-04 21:04:22 +00:00
pci
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
ps2
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
riscv
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
serial
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
sparc
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
storage
misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
2021-07-24 21:57:04 +00:00
virtio
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
x86
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
baddev.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
baddev.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
BadDevice.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Device.py
dev,dev-hsa,gpu-compute: Refactor dmaVirt calls
2021-07-09 22:40:18 +00:00
dma_device.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dma_device.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dma_virt_device.cc
dev,dev-hsa,gpu-compute: Refactor dmaVirt calls
2021-07-09 22:40:18 +00:00
dma_virt_device.hh
dev,dev-hsa,gpu-compute: Refactor dmaVirt calls
2021-07-09 22:40:18 +00:00
intel_8254_timer.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
intel_8254_timer.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
intpin.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
intpin.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
IntPin.py
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
io_device.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
io_device.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_fake.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_fake.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mc146818.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mc146818.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pixelpump.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pixelpump.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
platform.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
platform.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Platform.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_bank.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
reg_bank.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
rtcreg.h
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
SConscript
dev,dev-hsa,gpu-compute: Refactor dmaVirt calls
2021-07-09 22:40:18 +00:00