fb663678e6
This was mostly not used to begin with, but also when it was used, it would obscure places where there were types, functions, etc, which were switched between ISAs at compile time, and which would need to be cleaned up to allow more than one ISA at a time. Change-Id: Ieb372feff91b7e946b477fb78e54bcd0c2138966 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39655 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
707 lines
27 KiB
C++
707 lines
27 KiB
C++
/*
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* Copyright (c) 2011, 2016 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_CHECKER_CPU_IMPL_HH__
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#define __CPU_CHECKER_CPU_IMPL_HH__
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#include <list>
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#include <string>
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#include "base/refcnt.hh"
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#include "config/the_isa.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/reg_class.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/checker/cpu.hh"
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#include "debug/Checker.hh"
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#include "sim/full_system.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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template <class Impl>
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void
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Checker<Impl>::advancePC(const Fault &fault)
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{
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if (fault != NoFault) {
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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fault->invoke(tc, curStaticInst);
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thread->decoder.reset();
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} else {
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if (curStaticInst) {
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if (curStaticInst->isLastMicroop())
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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TheISA::PCState pcState = thread->pcState();
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TheISA::advancePC(pcState, curStaticInst);
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thread->pcState(pcState);
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DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
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}
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}
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}
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//////////////////////////////////////////////////
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template <class Impl>
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void
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Checker<Impl>::handlePendingInt()
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{
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DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
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thread->pcState(), instList.size());
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DynInstPtr boundaryInst = NULL;
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if (!instList.empty()) {
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// Set the instructions as completed and verify as much as possible.
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DynInstPtr inst;
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typename std::list<DynInstPtr>::iterator itr;
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for (itr = instList.begin(); itr != instList.end(); itr++) {
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(*itr)->setCompleted();
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}
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inst = instList.front();
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boundaryInst = instList.back();
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verify(inst); // verify the instructions
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inst = NULL;
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}
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if ((!boundaryInst && curMacroStaticInst &&
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curStaticInst->isDelayedCommit() &&
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!curStaticInst->isLastMicroop()) ||
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(boundaryInst && boundaryInst->isDelayedCommit() &&
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!boundaryInst->isLastMicroop())) {
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panic("%lli: Trying to take an interrupt in middle of "
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"a non-interuptable instruction!", curTick());
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}
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boundaryInst = NULL;
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thread->decoder.reset();
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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}
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template <class Impl>
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void
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Checker<Impl>::verify(const DynInstPtr &completed_inst)
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{
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DynInstPtr inst;
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// Make sure serializing instructions are actually
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// seen as serializing to commit. instList should be
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// empty in these cases.
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if ((completed_inst->isSerializing() ||
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completed_inst->isSerializeBefore()) &&
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(!instList.empty() ?
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(instList.front()->seqNum != completed_inst->seqNum) : 0)) {
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panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
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" entering instList with other instructions\n", curTick(),
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completed_inst->seqNum, completed_inst->pcState());
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}
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// Either check this instruction, or add it to a list of
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// instructions waiting to be checked. Instructions must be
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// checked in program order, so if a store has committed yet not
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// completed, there may be some instructions that are waiting
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// behind it that have completed and must be checked.
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if (!instList.empty()) {
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if (youngestSN < completed_inst->seqNum) {
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DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
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completed_inst->seqNum, completed_inst->pcState());
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instList.push_back(completed_inst);
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youngestSN = completed_inst->seqNum;
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}
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if (!instList.front()->isCompleted()) {
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return;
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} else {
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inst = instList.front();
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instList.pop_front();
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}
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} else {
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if (!completed_inst->isCompleted()) {
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if (youngestSN < completed_inst->seqNum) {
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DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
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completed_inst->seqNum, completed_inst->pcState());
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instList.push_back(completed_inst);
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youngestSN = completed_inst->seqNum;
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}
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return;
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} else {
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if (youngestSN < completed_inst->seqNum) {
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inst = completed_inst;
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youngestSN = completed_inst->seqNum;
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} else {
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return;
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}
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}
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}
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// Make sure a serializing instruction is actually seen as
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// serializing. instList should be empty here
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if (inst->isSerializeAfter() && !instList.empty()) {
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panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
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" exiting instList with other instructions\n", curTick(),
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completed_inst->seqNum, completed_inst->pcState());
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}
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unverifiedInst = inst;
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inst = NULL;
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// Try to check all instructions that are completed, ending if we
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// run out of instructions to check or if an instruction is not
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// yet completed.
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while (1) {
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DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
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unverifiedInst->seqNum, unverifiedInst->pcState());
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unverifiedReq = NULL;
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unverifiedReq = unverifiedInst->reqToVerify;
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unverifiedMemData = unverifiedInst->memData;
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// Make sure results queue is empty
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while (!result.empty()) {
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result.pop();
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}
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baseStats.numCycles++;
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Fault fault = NoFault;
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// maintain $r0 semantics
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thread->setIntReg(TheISA::ZeroReg, 0);
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// Check if any recent PC changes match up with anything we
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// expect to happen. This is mostly to check if traps or
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// PC-based events have occurred in both the checker and CPU.
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if (changedPC) {
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DPRINTF(Checker, "Changed PC recently to %s\n",
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thread->pcState());
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if (willChangePC) {
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if (newPCState == thread->pcState()) {
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DPRINTF(Checker, "Changed PC matches expected PC\n");
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} else {
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warn("%lli: Changed PC does not match expected PC, "
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"changed: %s, expected: %s",
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curTick(), thread->pcState(), newPCState);
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CheckerCPU::handleError();
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}
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willChangePC = false;
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}
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changedPC = false;
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}
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// Try to fetch the instruction
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uint64_t fetchOffset = 0;
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bool fetchDone = false;
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while (!fetchDone) {
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Addr fetch_PC = thread->instAddr();
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fetch_PC = (fetch_PC & PCMask) + fetchOffset;
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MachInst machInst;
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// If not in the middle of a macro instruction
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if (!curMacroStaticInst) {
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// set up memory request for instruction fetch
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auto mem_req = std::make_shared<Request>(
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fetch_PC, sizeof(MachInst), 0, requestorId, fetch_PC,
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thread->contextId());
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mem_req->setVirt(fetch_PC, sizeof(MachInst),
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Request::INST_FETCH, requestorId,
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thread->instAddr());
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fault = mmu->translateFunctional(
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mem_req, tc, BaseTLB::Execute);
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if (fault != NoFault) {
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if (unverifiedInst->getFault() == NoFault) {
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// In this case the instruction was not a dummy
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// instruction carrying an ITB fault. In the single
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// threaded case the ITB should still be able to
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// translate this instruction; in the SMT case it's
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// possible that its ITB entry was kicked out.
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warn("%lli: Instruction PC %s was not found in the "
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"ITB!", curTick(), thread->pcState());
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handleError(unverifiedInst);
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// go to the next instruction
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advancePC(NoFault);
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// Give up on an ITB fault..
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unverifiedInst = NULL;
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return;
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} else {
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// The instruction is carrying an ITB fault. Handle
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// the fault and see if our results match the CPU on
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// the next tick().
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fault = unverifiedInst->getFault();
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break;
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}
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} else {
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PacketPtr pkt = new Packet(mem_req, MemCmd::ReadReq);
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pkt->dataStatic(&machInst);
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icachePort->sendFunctional(pkt);
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delete pkt;
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}
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}
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if (fault == NoFault) {
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TheISA::PCState pcState = thread->pcState();
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if (isRomMicroPC(pcState.microPC())) {
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fetchDone = true;
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curStaticInst = thread->decoder.fetchRomMicroop(
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pcState.microPC(), nullptr);
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} else if (!curMacroStaticInst) {
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//We're not in the middle of a macro instruction
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StaticInstPtr instPtr = nullptr;
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//Predecode, ie bundle up an ExtMachInst
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//If more fetch data is needed, pass it in.
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Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
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thread->decoder.moreBytes(pcState, fetchPC, machInst);
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//If an instruction is ready, decode it.
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//Otherwise, we'll have to fetch beyond the
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//MachInst at the current pc.
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if (thread->decoder.instReady()) {
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fetchDone = true;
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instPtr = thread->decoder.decode(pcState);
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thread->pcState(pcState);
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} else {
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fetchDone = false;
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fetchOffset += sizeof(TheISA::MachInst);
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}
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//If we decoded an instruction and it's microcoded,
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//start pulling out micro ops
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if (instPtr && instPtr->isMacroop()) {
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curMacroStaticInst = instPtr;
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curStaticInst =
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instPtr->fetchMicroop(pcState.microPC());
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} else {
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curStaticInst = instPtr;
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}
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} else {
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// Read the next micro op from the macro-op
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curStaticInst =
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curMacroStaticInst->fetchMicroop(pcState.microPC());
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fetchDone = true;
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}
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}
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}
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// reset decoder on Checker
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thread->decoder.reset();
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// Check Checker and CPU get same instruction, and record
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// any faults the CPU may have had.
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Fault unverifiedFault;
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if (fault == NoFault) {
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unverifiedFault = unverifiedInst->getFault();
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// Checks that the instruction matches what we expected it to be.
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// Checks both the machine instruction and the PC.
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validateInst(unverifiedInst);
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}
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// keep an instruction count
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numInst++;
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// Either the instruction was a fault and we should process the fault,
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// or we should just go ahead execute the instruction. This assumes
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// that the instruction is properly marked as a fault.
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if (fault == NoFault) {
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// Execute Checker instruction and trace
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if (!unverifiedInst->isUnverifiable()) {
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Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
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tc,
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curStaticInst,
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pcState(),
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curMacroStaticInst);
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fault = curStaticInst->execute(this, traceData);
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if (traceData) {
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traceData->dump();
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delete traceData;
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}
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}
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if (fault == NoFault && unverifiedFault == NoFault) {
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thread->funcExeInst++;
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// Checks to make sure instrution results are correct.
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validateExecution(unverifiedInst);
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if (curStaticInst->isLoad()) {
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++numLoad;
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}
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} else if (fault != NoFault && unverifiedFault == NoFault) {
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panic("%lli: sn: %lli at PC: %s took a fault in checker "
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"but not in driver CPU\n", curTick(),
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unverifiedInst->seqNum, unverifiedInst->pcState());
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} else if (fault == NoFault && unverifiedFault != NoFault) {
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panic("%lli: sn: %lli at PC: %s took a fault in driver "
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"CPU but not in checker\n", curTick(),
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unverifiedInst->seqNum, unverifiedInst->pcState());
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}
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}
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// Take any faults here
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if (fault != NoFault) {
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if (FullSystem) {
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fault->invoke(tc, curStaticInst);
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willChangePC = true;
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newPCState = thread->pcState();
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DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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}
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} else {
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advancePC(fault);
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}
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if (FullSystem) {
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// @todo: Determine if these should happen only if the
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// instruction hasn't faulted. In the SimpleCPU case this may
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// not be true, but in the O3 case this may be true.
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Addr oldpc;
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int count = 0;
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do {
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oldpc = thread->instAddr();
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thread->pcEventQueue.service(oldpc, tc);
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count++;
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} while (oldpc != thread->instAddr());
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if (count > 1) {
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willChangePC = true;
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newPCState = thread->pcState();
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DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
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}
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}
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// @todo: Optionally can check all registers. (Or just those
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// that have been modified).
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validateState();
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// Continue verifying instructions if there's another completed
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// instruction waiting to be verified.
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if (instList.empty()) {
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break;
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} else if (instList.front()->isCompleted()) {
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unverifiedInst = NULL;
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unverifiedInst = instList.front();
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instList.pop_front();
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} else {
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break;
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}
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}
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unverifiedInst = NULL;
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}
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template <class Impl>
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void
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Checker<Impl>::switchOut()
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{
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instList.clear();
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}
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template <class Impl>
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void
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Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
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{
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}
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template <class Impl>
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void
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Checker<Impl>::validateInst(const DynInstPtr &inst)
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{
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if (inst->instAddr() != thread->instAddr()) {
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warn("%lli: PCs do not match! Inst: %s, checker: %s",
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curTick(), inst->pcState(), thread->pcState());
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if (changedPC) {
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warn("%lli: Changed PCs recently, may not be an error",
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curTick());
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} else {
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handleError(inst);
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}
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}
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if (curStaticInst != inst->staticInst) {
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warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
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curStaticInst->getName(), inst->staticInst->getName());
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}
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}
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template <class Impl>
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void
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Checker<Impl>::validateExecution(const DynInstPtr &inst)
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{
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InstResult checker_val;
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InstResult inst_val;
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int idx = -1;
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bool result_mismatch = false;
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bool scalar_mismatch = false;
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bool vector_mismatch = false;
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if (inst->isUnverifiable()) {
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// Unverifiable instructions assume they were executed
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// properly by the CPU. Grab the result from the
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// instruction and write it to the register.
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copyResult(inst, InstResult(0ul, InstResult::ResultType::Scalar), idx);
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} else if (inst->numDestRegs() > 0 && !result.empty()) {
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DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
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inst->numDestRegs(), result.size());
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for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
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checker_val = result.front();
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result.pop();
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inst_val = inst->popResult(
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InstResult(0ul, InstResult::ResultType::Scalar));
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if (checker_val != inst_val) {
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result_mismatch = true;
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idx = i;
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scalar_mismatch = checker_val.isScalar();
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vector_mismatch = checker_val.isVector();
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panic_if(!(scalar_mismatch || vector_mismatch),
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"Unknown type of result\n");
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}
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}
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} // Checker CPU checks all the saved results in the dyninst passed by
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// the cpu model being checked against the saved results present in
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// the static inst executed in the Checker. Sometimes the number
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|
// of saved results differs between the dyninst and static inst, but
|
|
// this is ok and not a bug. May be worthwhile to try and correct this.
|
|
|
|
if (result_mismatch) {
|
|
if (scalar_mismatch) {
|
|
warn("%lli: Instruction results (%i) do not match! (Values may"
|
|
" not actually be integers) Inst: %#x, checker: %#x",
|
|
curTick(), idx, inst_val.asIntegerNoAssert(),
|
|
checker_val.asInteger());
|
|
}
|
|
|
|
// It's useful to verify load values from memory, but in MP
|
|
// systems the value obtained at execute may be different than
|
|
// the value obtained at completion. Similarly DMA can
|
|
// present the same problem on even UP systems. Thus there is
|
|
// the option to only warn on loads having a result error.
|
|
// The load/store queue in Detailed CPU can also cause problems
|
|
// if load/store forwarding is allowed.
|
|
if (inst->isLoad() && warnOnlyOnLoadError) {
|
|
copyResult(inst, inst_val, idx);
|
|
} else {
|
|
handleError(inst);
|
|
}
|
|
}
|
|
|
|
if (inst->nextInstAddr() != thread->nextInstAddr()) {
|
|
warn("%lli: Instruction next PCs do not match! Inst: %#x, "
|
|
"checker: %#x",
|
|
curTick(), inst->nextInstAddr(), thread->nextInstAddr());
|
|
handleError(inst);
|
|
}
|
|
|
|
// Checking side effect registers can be difficult if they are not
|
|
// checked simultaneously with the execution of the instruction.
|
|
// This is because other valid instructions may have modified
|
|
// these registers in the meantime, and their values are not
|
|
// stored within the DynInst.
|
|
while (!miscRegIdxs.empty()) {
|
|
int misc_reg_idx = miscRegIdxs.front();
|
|
miscRegIdxs.pop();
|
|
|
|
if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
|
|
thread->readMiscRegNoEffect(misc_reg_idx)) {
|
|
warn("%lli: Misc reg idx %i (side effect) does not match! "
|
|
"Inst: %#x, checker: %#x",
|
|
curTick(), misc_reg_idx,
|
|
inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
|
|
thread->readMiscRegNoEffect(misc_reg_idx));
|
|
handleError(inst);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// This function is weird, if it is called it means the Checker and
|
|
// O3 have diverged, so panic is called for now. It may be useful
|
|
// to resynch states and continue if the divergence is a false positive
|
|
template <class Impl>
|
|
void
|
|
Checker<Impl>::validateState()
|
|
{
|
|
if (updateThisCycle) {
|
|
// Change this back to warn if divergences end up being false positives
|
|
panic("%lli: Instruction PC %#x results didn't match up, copying all "
|
|
"registers from main CPU", curTick(), unverifiedInst->instAddr());
|
|
|
|
// Terribly convoluted way to make sure O3 model does not implode
|
|
bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
|
|
unverifiedInst->thread->noSquashFromTC = true;
|
|
|
|
// Heavy-weight copying of all registers
|
|
thread->copyArchRegs(unverifiedInst->tcBase());
|
|
unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
|
|
|
|
// Set curStaticInst to unverifiedInst->staticInst
|
|
curStaticInst = unverifiedInst->staticInst;
|
|
// Also advance the PC. Hopefully no PC-based events happened.
|
|
advancePC(NoFault);
|
|
updateThisCycle = false;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
Checker<Impl>::copyResult(const DynInstPtr &inst,
|
|
const InstResult& mismatch_val, int start_idx)
|
|
{
|
|
// We've already popped one dest off the queue,
|
|
// so do the fix-up then start with the next dest reg;
|
|
if (start_idx >= 0) {
|
|
const RegId& idx = inst->destRegIdx(start_idx);
|
|
switch (idx.classValue()) {
|
|
case IntRegClass:
|
|
panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
|
|
thread->setIntReg(idx.index(), mismatch_val.asInteger());
|
|
break;
|
|
case FloatRegClass:
|
|
panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
|
|
thread->setFloatReg(idx.index(), mismatch_val.asInteger());
|
|
break;
|
|
case VecRegClass:
|
|
panic_if(!mismatch_val.isVector(), "Unexpected type of result");
|
|
thread->setVecReg(idx, mismatch_val.asVector());
|
|
break;
|
|
case VecElemClass:
|
|
panic_if(!mismatch_val.isVecElem(),
|
|
"Unexpected type of result");
|
|
thread->setVecElem(idx, mismatch_val.asVectorElem());
|
|
break;
|
|
case CCRegClass:
|
|
panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
|
|
thread->setCCReg(idx.index(), mismatch_val.asInteger());
|
|
break;
|
|
case MiscRegClass:
|
|
panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
|
|
thread->setMiscReg(idx.index(), mismatch_val.asInteger());
|
|
break;
|
|
default:
|
|
panic("Unknown register class: %d", (int)idx.classValue());
|
|
}
|
|
}
|
|
start_idx++;
|
|
InstResult res;
|
|
for (int i = start_idx; i < inst->numDestRegs(); i++) {
|
|
const RegId& idx = inst->destRegIdx(i);
|
|
res = inst->popResult();
|
|
switch (idx.classValue()) {
|
|
case IntRegClass:
|
|
panic_if(!res.isScalar(), "Unexpected type of result");
|
|
thread->setIntReg(idx.index(), res.asInteger());
|
|
break;
|
|
case FloatRegClass:
|
|
panic_if(!res.isScalar(), "Unexpected type of result");
|
|
thread->setFloatReg(idx.index(), res.asInteger());
|
|
break;
|
|
case VecRegClass:
|
|
panic_if(!res.isVector(), "Unexpected type of result");
|
|
thread->setVecReg(idx, res.asVector());
|
|
break;
|
|
case VecElemClass:
|
|
panic_if(!res.isVecElem(), "Unexpected type of result");
|
|
thread->setVecElem(idx, res.asVectorElem());
|
|
break;
|
|
case CCRegClass:
|
|
panic_if(!res.isScalar(), "Unexpected type of result");
|
|
thread->setCCReg(idx.index(), res.asInteger());
|
|
break;
|
|
case MiscRegClass:
|
|
panic_if(res.isValid(), "MiscReg expecting invalid result");
|
|
// Try to get the proper misc register index for ARM here...
|
|
thread->setMiscReg(idx.index(), 0);
|
|
break;
|
|
// else Register is out of range...
|
|
default:
|
|
panic("Unknown register class: %d", (int)idx.classValue());
|
|
}
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
Checker<Impl>::dumpAndExit(const DynInstPtr &inst)
|
|
{
|
|
cprintf("Error detected, instruction information:\n");
|
|
cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
|
"Completed:%i\n",
|
|
inst->pcState(),
|
|
inst->nextInstAddr(),
|
|
inst->seqNum,
|
|
inst->threadNumber,
|
|
inst->isCompleted());
|
|
inst->dump();
|
|
CheckerCPU::dumpAndExit();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
Checker<Impl>::dumpInsts()
|
|
{
|
|
int num = 0;
|
|
|
|
InstListIt inst_list_it = --(instList.end());
|
|
|
|
cprintf("Inst list size: %i\n", instList.size());
|
|
|
|
while (inst_list_it != instList.end())
|
|
{
|
|
cprintf("Instruction:%i\n",
|
|
num);
|
|
|
|
cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
|
|
"Completed:%i\n",
|
|
(*inst_list_it)->pcState(),
|
|
(*inst_list_it)->seqNum,
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->isCompleted());
|
|
|
|
cprintf("\n");
|
|
|
|
inst_list_it--;
|
|
++num;
|
|
}
|
|
|
|
}
|
|
|
|
#endif//__CPU_CHECKER_CPU_IMPL_HH__
|