e1db67c4bd
This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
805 lines
27 KiB
Python
805 lines
27 KiB
Python
# Copyright (c) 2010-2012, 2015-2019 ARM Limited
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# Copyright (c) 2020 Barkhausen Institut
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from common import ObjectList
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from common.Benchmarks import *
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import m5
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import m5.defines
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from m5.objects import *
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from m5.util import *
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# Populate to reflect supported os types per target ISA
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os_types = set()
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if m5.defines.buildEnv["USE_ARM_ISA"]:
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os_types.update(
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[
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"linux",
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"android-gingerbread",
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"android-ics",
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"android-jellybean",
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"android-kitkat",
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"android-nougat",
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]
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)
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if m5.defines.buildEnv["USE_MIPS_ISA"]:
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os_types.add("linux")
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if m5.defines.buildEnv["USE_POWER_ISA"]:
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os_types.add("linux")
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if m5.defines.buildEnv["USE_RISCV_ISA"]:
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os_types.add("linux") # TODO that's a lie
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if m5.defines.buildEnv["USE_SPARC_ISA"]:
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os_types.add("linux")
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if m5.defines.buildEnv["USE_X86_ISA"]:
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os_types.add("linux")
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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class MemBus(SystemXBar):
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badaddr_responder = BadAddr()
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default = Self.badaddr_responder.pio
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def attach_9p(parent, bus):
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viopci = PciVirtIO()
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viopci.vio = VirtIO9PDiod()
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viodir = os.path.realpath(os.path.join(m5.options.outdir, "9p"))
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viopci.vio.root = os.path.join(viodir, "share")
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viopci.vio.socketPath = os.path.join(viodir, "socket")
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os.makedirs(viopci.vio.root, exist_ok=True)
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if os.path.exists(viopci.vio.socketPath):
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os.remove(viopci.vio.socketPath)
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parent.viopci = viopci
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parent.attachPciDevice(viopci, bus)
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def fillInCmdline(mdesc, template, **kwargs):
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kwargs.setdefault("rootdev", mdesc.rootdev())
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kwargs.setdefault("mem", mdesc.mem())
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kwargs.setdefault("script", mdesc.script())
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return template % kwargs
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def makeCowDisks(disk_paths):
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disks = []
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for disk_path in disk_paths:
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disk = CowIdeDisk(driveID="device0")
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disk.childImage(disk_path)
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disks.append(disk)
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return disks
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def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
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# Constants from iob.cc and uart8250.cc
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iob_man_addr = 0x9800000000
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uart_pio_size = 8
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class CowMmDisk(MmDisk):
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image = CowDiskImage(
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child=RawDiskImage(read_only=True), read_only=False
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)
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def childImage(self, ci):
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self.image.child.image_file = ci
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self = System()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = IOXBar()
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self.membus = MemBus()
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self.bridge = Bridge(delay="50ns")
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self.t1000 = T1000()
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self.t1000.attachOnChipIO(self.membus)
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self.t1000.attachIO(self.iobus)
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self.mem_ranges = [
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AddrRange(Addr("1MiB"), size="64MiB"),
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AddrRange(Addr("2GiB"), size="256MiB"),
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]
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self.bridge.mem_side_port = self.iobus.cpu_side_ports
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self.bridge.cpu_side_port = self.membus.mem_side_ports
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self.disk0 = CowMmDisk()
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self.disk0.childImage(mdesc.disks()[0])
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self.disk0.pio = self.iobus.mem_side_ports
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# The puart0 and hvuart are placed on the IO bus, so create ranges
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# for them. The remaining IO range is rather fragmented, so poke
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# holes for the iob and partition descriptors etc.
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self.bridge.ranges = [
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AddrRange(
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self.t1000.puart0.pio_addr,
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self.t1000.puart0.pio_addr + uart_pio_size - 1,
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),
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AddrRange(
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self.disk0.pio_addr,
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self.t1000.fake_jbi.pio_addr + self.t1000.fake_jbi.pio_size - 1,
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),
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AddrRange(self.t1000.fake_clk.pio_addr, iob_man_addr - 1),
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AddrRange(
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self.t1000.fake_l2_1.pio_addr,
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self.t1000.fake_ssi.pio_addr + self.t1000.fake_ssi.pio_size - 1,
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),
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AddrRange(
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self.t1000.hvuart.pio_addr,
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self.t1000.hvuart.pio_addr + uart_pio_size - 1,
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),
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]
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workload = SparcFsWorkload()
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# ROM for OBP/Reset/Hypervisor
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self.rom = SimpleMemory(
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image_file=binary("t1000_rom.bin"),
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range=AddrRange(0xFFF0000000, size="8MiB"),
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)
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# nvram
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self.nvram = SimpleMemory(
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image_file=binary("nvram1"), range=AddrRange(0x1F11000000, size="8KiB")
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)
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# hypervisor description
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self.hypervisor_desc = SimpleMemory(
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image_file=binary("1up-hv.bin"),
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range=AddrRange(0x1F12080000, size="8KiB"),
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)
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# partition description
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self.partition_desc = SimpleMemory(
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image_file=binary("1up-md.bin"),
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range=AddrRange(0x1F12000000, size="8KiB"),
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)
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self.rom.port = self.membus.mem_side_ports
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self.nvram.port = self.membus.mem_side_ports
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self.hypervisor_desc.port = self.membus.mem_side_ports
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self.partition_desc.port = self.membus.mem_side_ports
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self.system_port = self.membus.cpu_side_ports
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self.workload = workload
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return self
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def makeArmSystem(
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mem_mode,
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machine_type,
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num_cpus=1,
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mdesc=None,
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dtb_filename=None,
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bare_metal=False,
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cmdline=None,
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external_memory="",
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ruby=False,
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vio_9p=None,
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bootloader=None,
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):
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assert machine_type
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pci_devices = []
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self = ArmSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = IOXBar()
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if not ruby:
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self.bridge = Bridge(delay="50ns")
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self.bridge.mem_side_port = self.iobus.cpu_side_ports
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self.membus = MemBus()
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self.membus.badaddr_responder.warn_access = "warn"
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self.bridge.cpu_side_port = self.membus.mem_side_ports
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self.mem_mode = mem_mode
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platform_class = ObjectList.platform_list.get(machine_type)
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# Resolve the real platform name, the original machine_type
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# variable might have been an alias.
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machine_type = platform_class.__name__
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self.realview = platform_class()
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self._bootmem = self.realview.bootmem
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# Attach any PCI devices this platform supports
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self.realview.attachPciDevices()
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disks = makeCowDisks(mdesc.disks())
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# Old platforms have a built-in IDE or CF controller. Default to
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# the IDE controller if both exist. New platforms expect the
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# storage controller to be added from the config script.
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if hasattr(self.realview, "ide"):
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self.realview.ide.disks = disks
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elif hasattr(self.realview, "cf_ctrl"):
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self.realview.cf_ctrl.disks = disks
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else:
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self.pci_ide = IdeController(disks=disks)
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pci_devices.append(self.pci_ide)
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self.mem_ranges = []
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size_remain = int(Addr(mdesc.mem()))
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for region in self.realview._mem_regions:
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if size_remain > int(region.size()):
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self.mem_ranges.append(region)
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size_remain = size_remain - int(region.size())
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else:
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self.mem_ranges.append(AddrRange(region.start, size=size_remain))
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size_remain = 0
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break
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warn(
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"Memory size specified spans more than one region. Creating"
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" another memory controller for that range."
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)
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if size_remain > 0:
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fatal(
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"The currently selected ARM platforms doesn't support"
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" the amount of DRAM you've selected. Please try"
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" another platform"
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)
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if bare_metal:
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# EOT character on UART will end the simulation
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self.realview.uart[0].end_on_eot = True
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self.workload = ArmFsWorkload(dtb_addr=0)
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else:
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workload = ArmFsLinux()
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if dtb_filename:
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workload.dtb_filename = binary(dtb_filename)
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workload.machine_type = (
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machine_type if machine_type in ArmMachineType.map else "DTOnly"
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)
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# Ensure that writes to the UART actually go out early in the boot
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if not cmdline:
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cmdline = (
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"earlyprintk=pl011,0x1c090000 console=ttyAMA0 "
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+ "lpj=19988480 norandmaps rw loglevel=8 "
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+ "mem=%(mem)s root=%(rootdev)s"
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)
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if hasattr(self.realview.gic, "cpu_addr"):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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# This check is for users who have previously put 'android' in
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# the disk image filename to tell the config scripts to
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# prepare the kernel with android-specific boot options. That
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# behavior has been replaced with a more explicit option per
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# the error message below. The disk can have any name now and
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# doesn't need to include 'android' substring.
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if mdesc.disks() and os.path.split(mdesc.disks()[0])[-1].lower().count(
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"android"
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):
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if "android" not in mdesc.os_type():
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fatal(
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"It looks like you are trying to boot an Android "
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"platform. To boot Android, you must specify "
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"--os-type with an appropriate Android release on "
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"the command line."
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)
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# android-specific tweaks
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if "android" in mdesc.os_type():
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# generic tweaks
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cmdline += " init=/init"
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# release-specific tweaks
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if "kitkat" in mdesc.os_type():
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cmdline += (
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" androidboot.hardware=gem5 qemu=1 qemu.gles=0 "
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+ "android.bootanim=0 "
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)
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elif "nougat" in mdesc.os_type():
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cmdline += (
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" androidboot.hardware=gem5 qemu=1 qemu.gles=0 "
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+ "android.bootanim=0 "
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+ "vmalloc=640MB "
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+ "android.early.fstab=/fstab.gem5 "
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+ "androidboot.selinux=permissive "
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+ "video=Virtual-1:1920x1080-16"
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)
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workload.command_line = fillInCmdline(mdesc, cmdline)
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self.workload = workload
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self.realview.setupBootLoader(self, binary, bootloader)
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if external_memory:
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# I/O traffic enters iobus
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self.external_io = ExternalMaster(
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port_data="external_io", port_type=external_memory
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)
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self.external_io.port = self.iobus.cpu_side_ports
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# Ensure iocache only receives traffic destined for (actual) memory.
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self.iocache = ExternalSlave(
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port_data="iocache",
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port_type=external_memory,
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addr_ranges=self.mem_ranges,
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)
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self.iocache.port = self.iobus.mem_side_ports
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# Let system_port get to nvmem and nothing else.
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self.bridge.ranges = [self.realview.nvmem.range]
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self.realview.attachOnChipIO(self.iobus)
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# Attach off-chip devices
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self.realview.attachIO(self.iobus)
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elif ruby:
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self._dma_ports = []
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self._mem_ports = []
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self.realview.attachOnChipIO(
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self.iobus, dma_ports=self._dma_ports, mem_ports=self._mem_ports
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)
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self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
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else:
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self.realview.attachOnChipIO(self.membus, self.bridge)
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# Attach off-chip devices
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self.realview.attachIO(self.iobus)
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for dev in pci_devices:
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self.realview.attachPciDevice(
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dev, self.iobus, dma_ports=self._dma_ports if ruby else None
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)
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self.terminal = Terminal()
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self.vncserver = VncServer()
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if vio_9p:
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attach_9p(self.realview, self.iobus)
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if not ruby:
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self.system_port = self.membus.cpu_side_ports
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if ruby:
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if buildEnv["PROTOCOL"] == "MI_example" and num_cpus > 1:
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fatal(
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"The MI_example protocol cannot implement Load/Store "
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"Exclusive operations. Multicore ARM systems configured "
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"with the MI_example protocol will not work properly."
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)
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return self
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def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
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class BaseMalta(Malta):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(
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disks=Parent.disks, pci_func=0, pci_dev=0, pci_bus=0
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)
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self = System()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = IOXBar()
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self.membus = MemBus()
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self.bridge = Bridge(delay="50ns")
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self.mem_ranges = [AddrRange("1GiB")]
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self.bridge.mem_side_port = self.iobus.cpu_side_ports
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self.bridge.cpu_side_port = self.membus.mem_side_ports
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self.disks = makeCowDisks(mdesc.disks())
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self.malta = BaseMalta()
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self.malta.attachIO(self.iobus)
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self.malta.ide.pio = self.iobus.mem_side_ports
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self.malta.ide.dma = self.iobus.cpu_side_ports
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self.malta.ethernet.pio = self.iobus.mem_side_ports
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self.malta.ethernet.dma = self.iobus.cpu_side_ports
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self.simple_disk = SimpleDisk(
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disk=RawDiskImage(image_file=mdesc.disks()[0], read_only=True)
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)
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.console = binary("mips/console")
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if not cmdline:
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cmdline = "root=/dev/hda1 console=ttyS0"
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self.workload = KernelWorkload(command_line=fillInCmdline(mdesc, cmdline))
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self.system_port = self.membus.cpu_side_ports
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return self
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def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port
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def connectX86ClassicSystem(x86_sys, numCPUs):
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# Constants similar to x86_traits.hh
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IO_address_space_base = 0x8000000000000000
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pci_config_address_space_base = 0xC000000000000000
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interrupts_address_space_base = 0xA000000000000000
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APIC_range_size = 1 << 12
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x86_sys.membus = MemBus()
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# North Bridge
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x86_sys.iobus = IOXBar()
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x86_sys.bridge = Bridge(delay="50ns")
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x86_sys.bridge.mem_side_port = x86_sys.iobus.cpu_side_ports
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x86_sys.bridge.cpu_side_port = x86_sys.membus.mem_side_ports
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# Allow the bridge to pass through:
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# 1) kernel configured PCI device memory map address: address range
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# [0xC0000000, 0xFFFF0000). (The upper 64KiB are reserved for m5ops.)
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# 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
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# 3) everything in the IO address range up to the local APIC, and
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# 4) then the entire PCI address space and beyond.
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x86_sys.bridge.ranges = [
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AddrRange(0xC0000000, 0xFFFF0000),
|
|
AddrRange(IO_address_space_base, interrupts_address_space_base - 1),
|
|
AddrRange(pci_config_address_space_base, Addr.max),
|
|
]
|
|
|
|
# Create a bridge from the IO bus to the memory bus to allow access to
|
|
# the local APIC (two pages)
|
|
x86_sys.apicbridge = Bridge(delay="50ns")
|
|
x86_sys.apicbridge.cpu_side_port = x86_sys.iobus.mem_side_ports
|
|
x86_sys.apicbridge.mem_side_port = x86_sys.membus.cpu_side_ports
|
|
x86_sys.apicbridge.ranges = [
|
|
AddrRange(
|
|
interrupts_address_space_base,
|
|
interrupts_address_space_base + numCPUs * APIC_range_size - 1,
|
|
)
|
|
]
|
|
|
|
# connect the io bus
|
|
x86_sys.pc.attachIO(x86_sys.iobus)
|
|
|
|
x86_sys.system_port = x86_sys.membus.cpu_side_ports
|
|
|
|
|
|
def connectX86RubySystem(x86_sys):
|
|
# North Bridge
|
|
x86_sys.iobus = IOXBar()
|
|
|
|
# add the ide to the list of dma devices that later need to attach to
|
|
# dma controllers
|
|
x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
|
|
x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
|
|
|
|
|
|
def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None, Ruby=False):
|
|
self = System()
|
|
|
|
self.m5ops_base = 0xFFFF0000
|
|
|
|
if workload is None:
|
|
workload = X86FsWorkload()
|
|
self.workload = workload
|
|
|
|
if not mdesc:
|
|
# generic system
|
|
mdesc = SysConfig()
|
|
self.readfile = mdesc.script()
|
|
|
|
self.mem_mode = mem_mode
|
|
|
|
# Physical memory
|
|
# On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
|
|
# for various devices. Hence, if the physical memory size is greater than
|
|
# 3GiB, we need to split it into two parts.
|
|
excess_mem_size = convert.toMemorySize(mdesc.mem()) - convert.toMemorySize(
|
|
"3GiB"
|
|
)
|
|
if excess_mem_size <= 0:
|
|
self.mem_ranges = [AddrRange(mdesc.mem())]
|
|
else:
|
|
warn(
|
|
"Physical memory size specified is %s which is greater than "
|
|
"3GiB. Twice the number of memory controllers would be "
|
|
"created." % (mdesc.mem())
|
|
)
|
|
|
|
self.mem_ranges = [
|
|
AddrRange("3GiB"),
|
|
AddrRange(Addr("4GiB"), size=excess_mem_size),
|
|
]
|
|
|
|
# Platform
|
|
self.pc = Pc()
|
|
|
|
# Create and connect the busses required by each memory system
|
|
if Ruby:
|
|
connectX86RubySystem(self)
|
|
else:
|
|
connectX86ClassicSystem(self, numCPUs)
|
|
|
|
# Disks
|
|
disks = makeCowDisks(mdesc.disks())
|
|
self.pc.south_bridge.ide.disks = disks
|
|
|
|
# Add in a Bios information structure.
|
|
structures = [X86SMBiosBiosInformation()]
|
|
workload.smbios_table.structures = structures
|
|
|
|
# Set up the Intel MP table
|
|
base_entries = []
|
|
ext_entries = []
|
|
madt_records = []
|
|
for i in range(numCPUs):
|
|
bp = X86IntelMPProcessor(
|
|
local_apic_id=i,
|
|
local_apic_version=0x14,
|
|
enable=True,
|
|
bootstrap=(i == 0),
|
|
)
|
|
base_entries.append(bp)
|
|
lapic = X86ACPIMadtLAPIC(acpi_processor_id=i, apic_id=i, flags=1)
|
|
madt_records.append(lapic)
|
|
io_apic = X86IntelMPIOAPIC(
|
|
id=numCPUs, version=0x11, enable=True, address=0xFEC00000
|
|
)
|
|
self.pc.south_bridge.io_apic.apic_id = io_apic.id
|
|
base_entries.append(io_apic)
|
|
madt_records.append(
|
|
X86ACPIMadtIOAPIC(id=io_apic.id, address=io_apic.address, int_base=0)
|
|
)
|
|
# In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
|
|
# but linux kernel cannot config PCI device if it was not connected to
|
|
# PCI bus, so we fix PCI bus id to 0, and ISA bus id to 1.
|
|
pci_bus = X86IntelMPBus(bus_id=0, bus_type="PCI ")
|
|
base_entries.append(pci_bus)
|
|
isa_bus = X86IntelMPBus(bus_id=1, bus_type="ISA ")
|
|
base_entries.append(isa_bus)
|
|
connect_busses = X86IntelMPBusHierarchy(
|
|
bus_id=1, subtractive_decode=True, parent_bus=0
|
|
)
|
|
ext_entries.append(connect_busses)
|
|
pci_dev4_inta = X86IntelMPIOIntAssignment(
|
|
interrupt_type="INT",
|
|
polarity="ConformPolarity",
|
|
trigger="ConformTrigger",
|
|
source_bus_id=0,
|
|
source_bus_irq=0 + (4 << 2),
|
|
dest_io_apic_id=io_apic.id,
|
|
dest_io_apic_intin=16,
|
|
)
|
|
base_entries.append(pci_dev4_inta)
|
|
pci_dev4_inta_madt = X86ACPIMadtIntSourceOverride(
|
|
bus_source=pci_dev4_inta.source_bus_id,
|
|
irq_source=pci_dev4_inta.source_bus_irq,
|
|
sys_int=pci_dev4_inta.dest_io_apic_intin,
|
|
flags=0,
|
|
)
|
|
madt_records.append(pci_dev4_inta_madt)
|
|
|
|
def assignISAInt(irq, apicPin):
|
|
assign_8259_to_apic = X86IntelMPIOIntAssignment(
|
|
interrupt_type="ExtInt",
|
|
polarity="ConformPolarity",
|
|
trigger="ConformTrigger",
|
|
source_bus_id=1,
|
|
source_bus_irq=irq,
|
|
dest_io_apic_id=io_apic.id,
|
|
dest_io_apic_intin=0,
|
|
)
|
|
base_entries.append(assign_8259_to_apic)
|
|
assign_to_apic = X86IntelMPIOIntAssignment(
|
|
interrupt_type="INT",
|
|
polarity="ConformPolarity",
|
|
trigger="ConformTrigger",
|
|
source_bus_id=1,
|
|
source_bus_irq=irq,
|
|
dest_io_apic_id=io_apic.id,
|
|
dest_io_apic_intin=apicPin,
|
|
)
|
|
base_entries.append(assign_to_apic)
|
|
# acpi
|
|
assign_to_apic_acpi = X86ACPIMadtIntSourceOverride(
|
|
bus_source=1, irq_source=irq, sys_int=apicPin, flags=0
|
|
)
|
|
madt_records.append(assign_to_apic_acpi)
|
|
|
|
assignISAInt(0, 2)
|
|
assignISAInt(1, 1)
|
|
for i in range(3, 15):
|
|
assignISAInt(i, i)
|
|
workload.intel_mp_table.base_entries = base_entries
|
|
workload.intel_mp_table.ext_entries = ext_entries
|
|
|
|
madt = X86ACPIMadt(
|
|
local_apic_address=0, records=madt_records, oem_id="madt"
|
|
)
|
|
workload.acpi_description_table_pointer.rsdt.entries.append(madt)
|
|
workload.acpi_description_table_pointer.xsdt.entries.append(madt)
|
|
workload.acpi_description_table_pointer.oem_id = "gem5"
|
|
workload.acpi_description_table_pointer.rsdt.oem_id = "gem5"
|
|
workload.acpi_description_table_pointer.xsdt.oem_id = "gem5"
|
|
return self
|
|
|
|
|
|
def makeLinuxX86System(
|
|
mem_mode, numCPUs=1, mdesc=None, Ruby=False, cmdline=None
|
|
):
|
|
# Build up the x86 system and then specialize it for Linux
|
|
self = makeX86System(mem_mode, numCPUs, mdesc, X86FsLinux(), Ruby)
|
|
|
|
# We assume below that there's at least 1MiB of memory. We'll require 2
|
|
# just to avoid corner cases.
|
|
phys_mem_size = sum([r.size() for r in self.mem_ranges])
|
|
assert phys_mem_size >= 0x200000
|
|
assert len(self.mem_ranges) <= 2
|
|
|
|
entries = [
|
|
# Mark the first mibibyte of memory as reserved
|
|
X86E820Entry(addr=0, size="639KiB", range_type=1),
|
|
X86E820Entry(addr=0x9FC00, size="385KiB", range_type=2),
|
|
# Mark the rest of physical memory as available
|
|
X86E820Entry(
|
|
addr=0x100000,
|
|
size="%dB" % (self.mem_ranges[0].size() - 0x100000),
|
|
range_type=1,
|
|
),
|
|
]
|
|
|
|
# Mark [mem_size, 3iB) as reserved if memory less than 3GiB, which force
|
|
# IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
|
|
# specific range can pass though bridge to iobus.
|
|
if len(self.mem_ranges) == 1:
|
|
entries.append(
|
|
X86E820Entry(
|
|
addr=self.mem_ranges[0].size(),
|
|
size="%dB" % (0xC0000000 - self.mem_ranges[0].size()),
|
|
range_type=2,
|
|
)
|
|
)
|
|
|
|
# Reserve the last 16KiB of the 32-bit address space for the m5op interface
|
|
entries.append(X86E820Entry(addr=0xFFFF0000, size="64KiB", range_type=2))
|
|
|
|
# In case the physical memory is greater than 3GiB, we split it into two
|
|
# parts and add a separate e820 entry for the second part. This entry
|
|
# starts at 0x100000000, which is the first address after the space
|
|
# reserved for devices.
|
|
if len(self.mem_ranges) == 2:
|
|
entries.append(
|
|
X86E820Entry(
|
|
addr=0x100000000,
|
|
size="%dB" % (self.mem_ranges[1].size()),
|
|
range_type=1,
|
|
)
|
|
)
|
|
|
|
self.workload.e820_table.entries = entries
|
|
|
|
# Command line
|
|
if not cmdline:
|
|
cmdline = "earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1"
|
|
self.workload.command_line = fillInCmdline(mdesc, cmdline)
|
|
return self
|
|
|
|
|
|
def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
|
|
self = System()
|
|
if not mdesc:
|
|
# generic system
|
|
mdesc = SysConfig()
|
|
self.mem_mode = mem_mode
|
|
self.mem_ranges = [AddrRange(mdesc.mem())]
|
|
|
|
self.workload = RiscvBareMetal()
|
|
|
|
self.iobus = IOXBar()
|
|
self.membus = MemBus()
|
|
|
|
self.bridge = Bridge(delay="50ns")
|
|
self.bridge.mem_side_port = self.iobus.cpu_side_ports
|
|
self.bridge.cpu_side_port = self.membus.mem_side_ports
|
|
# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO space
|
|
IO_address_space_base = 0x00FF000000000000
|
|
self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
|
|
|
|
self.system_port = self.membus.cpu_side_ports
|
|
return self
|
|
|
|
|
|
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
|
|
self = Root(full_system=full_system)
|
|
self.testsys = testSystem
|
|
self.drivesys = driveSystem
|
|
self.etherlink = EtherLink()
|
|
|
|
if hasattr(testSystem, "realview"):
|
|
self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
|
|
self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
|
|
elif hasattr(testSystem, "tsunami"):
|
|
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
|
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
|
|
else:
|
|
fatal("Don't know how to connect these system together")
|
|
|
|
if dumpfile:
|
|
self.etherdump = EtherDump(file=dumpfile)
|
|
self.etherlink.dump = Parent.etherdump
|
|
|
|
return self
|
|
|
|
|
|
def makeDistRoot(
|
|
testSystem,
|
|
rank,
|
|
size,
|
|
server_name,
|
|
server_port,
|
|
sync_repeat,
|
|
sync_start,
|
|
linkspeed,
|
|
linkdelay,
|
|
dumpfile,
|
|
):
|
|
self = Root(full_system=True)
|
|
self.testsys = testSystem
|
|
|
|
self.etherlink = DistEtherLink(
|
|
speed=linkspeed,
|
|
delay=linkdelay,
|
|
dist_rank=rank,
|
|
dist_size=size,
|
|
server_name=server_name,
|
|
server_port=server_port,
|
|
sync_start=sync_start,
|
|
sync_repeat=sync_repeat,
|
|
)
|
|
|
|
if hasattr(testSystem, "realview"):
|
|
self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
|
|
elif hasattr(testSystem, "tsunami"):
|
|
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
|
else:
|
|
fatal("Don't know how to connect DistEtherLink to this system")
|
|
|
|
if dumpfile:
|
|
self.etherdump = EtherDump(file=dumpfile)
|
|
self.etherlink.dump = Parent.etherdump
|
|
|
|
return self
|