Geoffrey Blake f9c54d5a4b Temporary fix for ll/sc bug see flyspray task for more info: ...

http://www.m5sim.org/flyspray/task/197

Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

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extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81

2008-01-06 00:19:45 -05:00

..

miss

Mark cache-to-cache MSHRs as downstreamPending when necessary.

2008-01-02 15:18:33 -08:00

prefetch

params: Deprecate old-style constructors; update most SimObject constructors.

2007-08-30 15:16:59 -04:00

tags

Cache: Fix for OS X 10.5 compiling.

2007-11-04 18:57:36 -05:00

base_cache.cc

Add functional PrintReq command for memory-system debugging.

2008-01-02 12:20:15 -08:00

base_cache.hh

Add functional PrintReq command for memory-system debugging.

2008-01-02 12:20:15 -08:00

BaseCache.py

DMA: Add IOCache and fix bus bridge to optionally only send requests one

2007-08-10 16:14:01 -04:00

cache_blk.cc

Add functional PrintReq command for memory-system debugging.

2008-01-02 12:20:15 -08:00

cache_blk.hh

Additional comments and helper functions for PrintReq.

2008-01-02 13:46:22 -08:00

cache_builder.cc

params: Deprecate old-style constructors; update most SimObject constructors.

2007-08-30 15:16:59 -04:00

cache_impl.hh

Temporary fix for ll/sc bug see flyspray task for more info:

2008-01-06 00:19:45 -05:00

cache.cc

Get rid of coherence protocol object.

2007-06-27 20:54:13 -07:00

cache.hh

Add ReadRespWithInvalidate to handle multi-level coherence situation

2008-01-02 15:22:38 -08:00

SConscript

Add functional PrintReq command for memory-system debugging.

2008-01-02 12:20:15 -08:00