Ron Dreslinski f89b56b61a Check the response queue on functional accesses. ...

The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?

src/mem/cache/base_cache.cc:
src/mem/tport.cc:
    Add in functional check of retry queued packets.

--HG--
extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a

2006-10-12 13:59:03 -04:00

..

arch

Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)

2006-10-08 10:53:24 -07:00

base

Fix problems with unCacheable addresses in timing-coherence

2006-10-12 13:33:21 -04:00

cpu

Another memleak in the memtester (need [] with the delete)

2006-10-12 13:45:28 -04:00

dev

post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.

2006-10-08 23:18:19 -04:00

doxygen

Fix up doxygen.

2006-08-14 19:25:07 -04:00

kern

Allocate new thread stacks and shared mem region via Process page table

2006-10-08 04:29:40 -04:00

mem

Check the response queue on functional accesses.

2006-10-12 13:59:03 -04:00

python

More cache fixes. Atomic coherence now works as well.

2006-10-11 18:28:33 -04:00

sim

Merge zizzer:/bk/newmem

2006-10-06 21:46:04 -04:00

unittest

Merge iceaxe.:/Volumes/work/research/m5/head

2006-06-11 22:01:34 -04:00

Doxyfile

Fix up doxygen.

2006-08-14 19:25:07 -04:00

SConscript

Two minor fixes.

2006-10-10 01:49:46 -04:00