f7d4ff6ef5
This changeset adds Vega support as a copy of GCN3. Configs have been modified to include both ISAs. Current implementation is not complete and needs modifications to fully comply with the ISA manual: https://developer.amd.com/wp-content/resources/ Vega_Shader_ISA_28July2017.pdf Change-Id: I608aa6747a45594f8e1bd7802da1883cf612168b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42204 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
95 lines
3.6 KiB
C++
95 lines
3.6 KiB
C++
/*
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* Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
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#define __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
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#include "arch/amdgpu/vega/gpu_registers.hh"
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#include "arch/amdgpu/vega/operand.hh"
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#include "gpu-compute/gpu_static_inst.hh"
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#include "gpu-compute/scalar_register_file.hh"
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#include "gpu-compute/vector_register_file.hh"
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#include "gpu-compute/wavefront.hh"
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namespace VegaISA
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{
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class VEGAGPUStaticInst : public GPUStaticInst
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{
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public:
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VEGAGPUStaticInst(const std::string &opcode);
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~VEGAGPUStaticInst();
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void generateDisassembly() override { disassembly = _opcode; }
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bool
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isFlatScratchRegister(int opIdx) override
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{
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return isFlatScratchReg(opIdx);
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}
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bool isScalarRegister(int opIdx) override { return false; }
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bool isVectorRegister(int opIdx) override { return false; }
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bool isSrcOperand(int opIdx) override { return false; }
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bool isDstOperand(int opIdx) override { return false; }
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int getOperandSize(int opIdx) override { return 0; }
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int
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getRegisterIndex(int opIdx, int num_scalar_regs) override
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{
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return 0;
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}
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/**
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* Return the number of tokens needed by the coalescer. In VEGA there
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* is generally one packet per memory request per lane generated. In
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* HSAIL, the number of dest operands is used for loads and src
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* operands for stores. This method should be overriden on a per-inst
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* basis when this value differs.
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*/
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int coalescerTokenCount() const override { return 1; }
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ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
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protected:
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void panicUnimplemented() const;
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/**
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* if the instruction has a src literal - an immediate
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* value that is part of the instruction stream - we
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* store that here
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*/
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ScalarRegU32 _srcLiteral;
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}; // class VEGAGPUStaticInst
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} // namespace VegaISA
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#endif //__ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
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