There has been some debate on how best to distribute the components library. This change builds the components library into the gem5 binary. The components library will now function similar to the `m5` library. There is no need for awkward imports or obtaining the library from some third-party source. Additional incorporated in this patch: * Added `__init__.py` to the Python modules. * Fixed a typo in the `abstract_ruby_cache_hierarchy.py` filename. * Ensured that imports within the library are relative. Issue-on: https://gem5.atlassian.net/browse/GEM5-1023 Change-Id: I3988c8710cda8dcf7b21109a2cf5c3f1608cc71a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49690 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Austin Harris <mail@austin-harris.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
138 lines
5.5 KiB
Python
138 lines
5.5 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from ..utils.override import overrides
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from ..boards.mem_mode import MemMode
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from .complex_generator_core import ComplexGeneratorCore
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from .abstract_processor import AbstractProcessor
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from ..boards.abstract_board import AbstractBoard
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class ComplexGenerator(AbstractProcessor):
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def __init__(self, num_cores: int = 1) -> None:
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super(ComplexGenerator, self).__init__(
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cores=[ComplexGeneratorCore() for i in range(num_cores)]
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)
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"""The complex generator
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This class defines an external interface to create a list of complex
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generator cores that could replace the processing cores in a board.
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:param num_cores: The number of complex generator cores to create.
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"""
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@overrides(AbstractProcessor)
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def incorporate_processor(self, board: AbstractBoard) -> None:
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board.set_mem_mode(MemMode.TIMING)
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def add_linear(
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self,
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duration: str = "1ms",
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rate: str = "100GB/s",
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block_size: int = 64,
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min_addr: int = 0,
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max_addr: int = 32768,
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rd_perc: int = 100,
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data_limit: int = 0,
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) -> None:
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"""
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This function will add a linear traffic to all the cores in the
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generator with the params specified.
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:param duration: The number of ticks for the generator core to generate
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traffic.
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:param rate: The rate at which the synthetic data is read/written.
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:param block_size: The number of bytes to be read/written with each
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request.
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:param min_addr: The lower bound of the address range the generator
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will read/write from/to.
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:param max_addr: The upper bound of the address range the generator
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will read/write from/to.
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:param rd_perc: The percentage of read requests among all the generated
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requests. The write percentage would be equal to 100 - rd_perc.
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:param data_limit: The amount of data in bytes to read/write by the
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generator before stopping generation.
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"""
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for core in self.cores:
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core.add_linear(
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duration,
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rate,
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block_size,
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min_addr,
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max_addr,
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rd_perc,
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data_limit,
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)
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def add_random(
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self,
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duration: str = "1ms",
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rate: str = "100GB/s",
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block_size: int = 64,
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min_addr: int = 0,
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max_addr: int = 32768,
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rd_perc: int = 100,
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data_limit: int = 0,
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) -> None:
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"""
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This function will add a random traffic to all the cores in the
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generator with the params specified.
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:param duration: The number of ticks for the generator core to generate
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traffic.
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:param rate: The rate at which the synthetic data is read/written.
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:param block_size: The number of bytes to be read/written with each
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request.
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:param min_addr: The lower bound of the address range the generator
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will read/write from/to.
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:param max_addr: The upper bound of the address range the generator
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will read/write from/to.
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:param rd_perc: The percentage of read requests among all the generated
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requests. The write percentage would be equal to 100 - rd_perc.
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:param data_limit: The amount of data in bytes to read/write by the
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generator before stopping generation.
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"""
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for core in self.cores:
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core.add_random(
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duration,
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rate,
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block_size,
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min_addr,
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max_addr,
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rd_perc,
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data_limit,
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)
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def start_traffic(self) -> None:
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"""
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This function will start the traffic at the top of the traffic list. It
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will also pop the first element so that the generator will start a
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new traffic everytime this is called.
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"""
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for core in self.cores:
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core.start_traffic()
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