Ivan Fernandez f6c61836b3 arch-riscv: adding vector unit-stride segment loads to RISC-V (#851) ...

This commit adds support for vector unit-stride segment load operations
for RISC-V (vlseg<NF>e<X>). This implementation is based in two types of
microops:
- VlSeg microops that load data as it is organized in memory in structs
of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into
destination registers.

Gem5 issue: https://github.com/gem5/gem5/issues/382

2024-03-06 11:27:06 -08:00

..

arch

arch-riscv: adding vector unit-stride segment loads to RISC-V (#851)

2024-03-06 11:27:06 -08:00

base

base: Add a check for edge case

2024-01-23 11:35:54 -08:00

cpu

arch-riscv: adding vector unit-stride segment loads to RISC-V (#851)

2024-03-06 11:27:06 -08:00

dev

dev: RegisterBank addRegistersAt for fragmented reg banks (#902)

2024-03-01 15:32:40 +00:00

doc

…

doxygen

…

gpu-compute

gpu-compute: Store accum_offset from code object in WF

2024-02-26 12:54:37 -06:00

kern

misc: Fix 'maybe-uninitialized' warn turn off (#706)

2023-12-21 18:45:56 -08:00

learning_gem5

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mem

mem-cache: Add support for partitioning caches (#765)

2024-03-04 09:44:01 +00:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

stdlib: Fix initialization for self.pic.hart_config in lupv_board (#904)

2024-03-01 11:25:00 -08:00

sim

sim-se: Catch None value if binary is not compatible with gem5 (#903)

2024-03-01 16:41:18 -08:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Reduce unnecessary backdoor request in atomic transaction (#795)

2024-02-05 11:08:20 -08:00

Doxyfile

misc: Change version information to develop for v24.0

2023-12-27 12:29:52 -08:00

Kconfig

scons: Add new config option HAVE_CAPSTONE to Kconfig

2023-11-23 08:26:11 +08:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00