823b5a6eb8
Currently gem5 assumes that there is only one command processor (CP) which contains the PM4 packet processor. Some GPU devices have multiple CPs which the driver tests individually during POST if they are used or not. Therefore, these additional CPs need to be supported. This commit allows for multiple PM4 packet processors which represent multiple CPs. Each of these processors will have its own independent MMIO address range. To more easily support ranges, the MMIO addresses now use AddrRange to index a PM4 packet processor instead of the hard-coded constexpr MMIO start and size pairs. By default only one PM4 packet processor is created, meaning the functionality of the simulation is unchanged for devices currently supported in gem5. Change-Id: I977f4fd3a169ef4a78671a4fb58c8ea0e19bf52c
373 lines
11 KiB
C++
373 lines
11 KiB
C++
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_AMDGPU_AMDGPU_VM_HH__
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#define __DEV_AMDGPU_AMDGPU_VM_HH__
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#include <vector>
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#include "arch/amdgpu/vega/pagetable_walker.hh"
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#include "base/intmath.hh"
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#include "dev/amdgpu/amdgpu_defines.hh"
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#include "mem/packet.hh"
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#include "mem/translation_gen.hh"
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#include "sim/serialize.hh"
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/**
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* MMIO offsets for graphics register bus manager (GRBM). These values were
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* taken from linux header files. The header files can be found here:
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*
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* https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
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* drivers/gpu/drm/amd/include/ asic_reg/gc/gc_9_0_offset.h
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* https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
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* drivers/gpu/drm/amd/include/ asic_reg/mmhub/mmhub_1_0_offset.h
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*/
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#define mmVM_INVALIDATE_ENG17_ACK 0x08c6
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#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb
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#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec
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#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b
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#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c
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#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b
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#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c
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#define mmMC_VM_FB_OFFSET 0x096b
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#define mmMC_VM_FB_LOCATION_BASE 0x0980
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#define mmMC_VM_FB_LOCATION_TOP 0x0981
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#define mmMC_VM_AGP_TOP 0x0982
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#define mmMC_VM_AGP_BOT 0x0983
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#define mmMC_VM_AGP_BASE 0x0984
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#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985
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#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986
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#define mmMMHUB_VM_INVALIDATE_ENG17_SEM 0x06e2
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#define mmMMHUB_VM_INVALIDATE_ENG17_REQ 0x06f4
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#define mmMMHUB_VM_INVALIDATE_ENG17_ACK 0x0706
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#define mmMMHUB_VM_FB_LOCATION_BASE 0x082c
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#define mmMMHUB_VM_FB_LOCATION_TOP 0x082d
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#define VEGA10_FB_LOCATION_BASE 0x6a0b0
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#define VEGA10_FB_LOCATION_TOP 0x6a0b4
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#define MI100_MEM_SIZE_REG 0x0378c
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#define MI100_FB_LOCATION_BASE 0x6ac00
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#define MI100_FB_LOCATION_TOP 0x6ac04
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#define MI200_MEM_SIZE_REG 0x0378c
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#define MI200_FB_LOCATION_BASE 0x6b300
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#define MI200_FB_LOCATION_TOP 0x6b304
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// AMD GPUs support 16 different virtual address spaces
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static constexpr int AMDGPU_VM_COUNT = 16;
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// These apertures have a fixed page size
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static constexpr int AMDGPU_AGP_PAGE_SIZE = 4096;
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static constexpr int AMDGPU_GART_PAGE_SIZE = 4096;
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static constexpr int AMDGPU_MMHUB_PAGE_SIZE = 4096;
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// Vega page size can be any power of 2 between 4kB and 1GB.
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static constexpr int AMDGPU_USER_PAGE_SIZE = 4096;
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namespace gem5
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{
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typedef enum : int
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{
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NBIO_MMIO_RANGE,
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MMHUB_MMIO_RANGE,
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GFX_MMIO_RANGE,
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GRBM_MMIO_RANGE,
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IH_MMIO_RANGE,
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NUM_MMIO_RANGES
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} mmio_range_t;
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class AMDGPUDevice;
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class AMDGPUVM : public Serializable
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{
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private:
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AMDGPUDevice *gpuDevice;
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typedef struct GEM5_PACKED
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{
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// Page table addresses: from (Base + Start) to (End)
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union
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{
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struct
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{
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uint32_t ptBaseL;
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uint32_t ptBaseH;
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};
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Addr ptBase;
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};
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union
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{
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struct
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{
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uint32_t ptStartL;
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uint32_t ptStartH;
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};
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Addr ptStart;
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};
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union
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{
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struct
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{
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uint32_t ptEndL;
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uint32_t ptEndH;
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};
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Addr ptEnd;
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};
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} AMDGPUVMContext;
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typedef struct AMDGPUSysVMContext : AMDGPUVMContext
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{
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Addr agpBase;
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Addr agpTop;
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Addr agpBot;
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Addr fbBase;
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Addr fbTop;
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Addr fbOffset;
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Addr sysAddrL;
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Addr sysAddrH;
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} AMDGPUSysVMContext;
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AMDGPUSysVMContext vmContext0;
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std::vector<AMDGPUVMContext> vmContexts;
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// MMHUB aperture. These addresses mirror the framebuffer, so addresses
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// can be calculated by subtracting the base address.
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uint64_t mmhubBase = 0x0;
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uint64_t mmhubTop = 0x0;
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/**
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* List of TLBs associated with the GPU device. This is used for flushing
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* the TLBs upon a driver request.
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*/
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std::vector<VegaISA::GpuTLB *> gpu_tlbs;
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std::array<AddrRange, NUM_MMIO_RANGES> mmioRanges;
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public:
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AMDGPUVM();
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void setGPUDevice(AMDGPUDevice *gpu_device) { gpuDevice = gpu_device; }
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/**
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* Return base address of GART table in framebuffer.
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*/
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Addr gartBase();
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/**
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* Return size of GART in number of PTEs.
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*/
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Addr gartSize();
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bool
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inGARTRange(Addr paddr)
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{
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return ((paddr >= gartBase()) && (paddr <= (gartBase() + gartSize())));
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}
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/**
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* Copy of GART table. Typically resides in device memory, however we use
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* a copy in gem5 to simplify the interface.
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*/
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std::unordered_map<uint64_t, uint64_t> gartTable;
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void readMMIO(PacketPtr pkt, Addr offset);
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void writeMMIO(PacketPtr pkt, Addr offset);
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/**
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* Methods for resolving apertures
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*/
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bool
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inAGP(Addr vaddr)
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{
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return ((vaddr >= vmContext0.agpBot) && (vaddr <= vmContext0.agpTop));
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}
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Addr getAGPBot() { return vmContext0.agpBot; }
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Addr getAGPTop() { return vmContext0.agpTop; }
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Addr getAGPBase() { return vmContext0.agpBase; }
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bool
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inMMHUB(Addr vaddr)
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{
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return ((vaddr >= getMMHUBBase()) && (vaddr <= getMMHUBTop()));
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}
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Addr getMMHUBBase() { return mmhubBase; }
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Addr getMMHUBTop() { return mmhubTop; }
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void setMMHUBBase(Addr base) { mmhubBase = base; }
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void setMMHUBTop(Addr top) { mmhubTop = top; }
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bool
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inFB(Addr vaddr)
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{
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return ((vaddr >= vmContext0.fbBase) && (vaddr <= vmContext0.fbTop));
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}
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Addr getFBBase() { return vmContext0.fbBase; }
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Addr getFBTop() { return vmContext0.fbTop; }
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Addr getFBOffset() { return vmContext0.fbOffset; }
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bool
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inSys(Addr vaddr)
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{
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return ((vaddr >= vmContext0.sysAddrL) &&
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(vaddr <= vmContext0.sysAddrH));
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}
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Addr getSysAddrRangeLow () { return vmContext0.sysAddrL; }
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Addr getSysAddrRangeHigh () { return vmContext0.sysAddrH; }
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void setMMIOAperture(mmio_range_t mmio_aperture, AddrRange range);
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const AddrRange& getMMIOAperture(Addr addr);
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AddrRange getMMIORange(mmio_range_t mmio_aperture);
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// Getting mapped aperture base addresses
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Addr
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getFrameAperture(Addr addr)
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{
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if (addr < gartBase()) {
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warn_once("Accessing unsupported frame apperture!\n");
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return ~0;
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} else if (gartBase() <= addr && addr < (gartBase() + gartSize())) {
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return gartBase();
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} else {
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warn_once("Accessing unsupported frame apperture!\n");
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return ~0;
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}
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}
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/**
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* Page table base/start accessors for user VMIDs.
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*/
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void
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setPageTableBase(uint16_t vmid, Addr ptBase)
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{
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vmContexts[vmid].ptBase = ptBase;
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}
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Addr
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getPageTableBase(uint16_t vmid)
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{
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assert(vmid > 0 && vmid < vmContexts.size());
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return vmContexts[vmid].ptBase;
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}
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Addr
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getPageTableStart(uint16_t vmid)
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{
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assert(vmid > 0 && vmid < vmContexts.size());
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return vmContexts[vmid].ptStart;
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}
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/**
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* Control methods for TLBs associated with the GPU device.
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*/
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void registerTLB(VegaISA::GpuTLB *tlb);
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void invalidateTLBs();
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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/**
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* Translation range generators
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*
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* AGP - Legacy interface to device memory. Addr range is set via MMIO
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* GART - Legacy privledged translation table. Table in device memory
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* MMHUB - Shadow range of VRAM
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*/
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class AGPTranslationGen : public TranslationGen
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{
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private:
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AMDGPUVM *vm;
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void translate(Range &range) const override;
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public:
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AGPTranslationGen(AMDGPUVM *_vm, Addr vaddr, Addr size)
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: TranslationGen(vaddr, size), vm(_vm)
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{}
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};
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class GARTTranslationGen : public TranslationGen
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{
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private:
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AMDGPUVM *vm;
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void translate(Range &range) const override;
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public:
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GARTTranslationGen(AMDGPUVM *_vm, Addr vaddr, Addr size)
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: TranslationGen(vaddr, size), vm(_vm)
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{}
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};
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class MMHUBTranslationGen : public TranslationGen
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{
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private:
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AMDGPUVM *vm;
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void translate(Range &range) const override;
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public:
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MMHUBTranslationGen(AMDGPUVM *_vm, Addr vaddr, Addr size)
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: TranslationGen(vaddr, size), vm(_vm)
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{}
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};
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class UserTranslationGen : public TranslationGen
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{
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private:
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AMDGPUVM *vm;
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VegaISA::Walker *walker;
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int vmid;
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void translate(Range &range) const override;
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public:
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UserTranslationGen(AMDGPUVM *_vm, VegaISA::Walker *_walker, int _vmid,
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Addr vaddr, Addr size)
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: TranslationGen(vaddr, size), vm(_vm), walker(_walker),
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vmid(_vmid)
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{}
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};
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};
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} // namespace gem5
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#endif // __DEV_AMDGPU_AMDGPU_VM_HH__
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