9313294efe
Remove the line "For use for simulation and test purposes only" in files were AMD is the only copyright holder listed in the header. This happens to be the case for all files where this line exists, removing it completely from gem5. Change-Id: I623f266b002f564301b28774f49081099cfc60fd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53943 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
360 lines
12 KiB
Python
360 lines
12 KiB
Python
# Copyright (c) 2018-2021 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, argparse, sys
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addToPath('../')
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from common import Options
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from ruby import Ruby
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#
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# Add the ruby specific and protocol specific options
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#
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parser = argparse.ArgumentParser()
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Options.addNoISAOptions(parser)
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Ruby.define_options(parser)
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# GPU Ruby tester options
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parser.add_argument("--cache-size", default="small",
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choices=["small", "large"],
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help="Cache sizes to use. Small encourages races between \
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requests and writebacks. Large stresses write-through \
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and/or write-back GPU caches.")
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parser.add_argument("--system-size", default="small",
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choices=["small", "medium", "large"],
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help="This option defines how many CUs, CPUs and cache \
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components in the test system.")
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parser.add_argument("--address-range", default="small",
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choices=["small", "large"],
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help="This option defines the number of atomic \
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locations that affects the working set's size. \
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A small number of atomic locations encourage more \
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races among threads. The large option stresses cache \
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resources.")
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parser.add_argument("--episode-length", default="short",
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choices=["short", "medium", "long"],
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help="This option defines the number of LDs and \
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STs in an episode. The small option encourages races \
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between the start and end of an episode. The long \
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option encourages races between LDs and STs in the \
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same episode.")
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parser.add_argument("--test-length", type=int, default=1,
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help="The number of episodes to be executed by each \
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wavefront. This determines the maximum number, i.e., \
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val X #WFs, of episodes to be executed in the test.")
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parser.add_argument("--debug-tester", action='store_true',
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help="This option will turn on DRF checker")
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parser.add_argument("--random-seed", type=int, default=0,
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help="Random seed number. Default value (i.e., 0) means \
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using runtime-specific value")
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parser.add_argument("--log-file", type=str, default="gpu-ruby-test.log")
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parser.add_argument("--num-dmas", type=int, default=0,
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help="The number of DMA engines to use in tester config.")
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args = parser.parse_args()
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#
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# Set up cache size - 2 options
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# 0: small cache
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# 1: large cache
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#
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if (args.cache_size == "small"):
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args.tcp_size="256B"
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args.tcp_assoc=2
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args.tcc_size="1kB"
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args.tcc_assoc=2
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elif (args.cache_size == "large"):
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args.tcp_size="256kB"
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args.tcp_assoc=16
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args.tcc_size="1024kB"
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args.tcc_assoc=16
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#
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# Set up system size - 3 options
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#
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if (args.system_size == "small"):
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# 1 CU, 1 CPU, 1 SQC, 1 Scalar
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args.wf_size = 1
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args.wavefronts_per_cu = 1
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args.num_cpus = 1
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args.num_dmas = 1
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args.cu_per_sqc = 1
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args.cu_per_scalar_cache = 1
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args.num_compute_units = 1
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elif (args.system_size == "medium"):
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# 4 CUs, 4 CPUs, 1 SQCs, 1 Scalars
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args.wf_size = 16
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args.wavefronts_per_cu = 4
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args.num_cpus = 4
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args.num_dmas = 2
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args.cu_per_sqc = 4
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args.cu_per_scalar_cache = 4
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args.num_compute_units = 4
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elif (args.system_size == "large"):
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# 8 CUs, 4 CPUs, 1 SQCs, 1 Scalars
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args.wf_size = 32
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args.wavefronts_per_cu = 4
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args.num_cpus = 4
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args.num_dmas = 4
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args.cu_per_sqc = 4
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args.cu_per_scalar_cache = 4
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args.num_compute_units = 8
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#
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# Set address range - 2 options
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# level 0: small
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# level 1: large
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# Each location corresponds to a 4-byte piece of data
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#
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args.mem_size = '1024MB'
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if (args.address_range == "small"):
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num_atomic_locs = 10
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num_regular_locs_per_atomic_loc = 10000
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elif (args.address_range == "large"):
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num_atomic_locs = 100
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num_regular_locs_per_atomic_loc = 100000
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#
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# Set episode length (# of actions per episode) - 3 options
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# 0: 10 actions
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# 1: 100 actions
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# 2: 500 actions
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#
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if (args.episode_length == "short"):
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eps_length = 10
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elif (args.episode_length == "medium"):
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eps_length = 100
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elif (args.episode_length == "long"):
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eps_length = 500
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#
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# Set Ruby and tester deadlock thresholds. Ruby's deadlock detection is the
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# primary check for deadlocks. The tester's deadlock threshold detection is
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# a secondary check for deadlock. If there is a bug in RubyPort that causes
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# a packet not to return to the tester properly, the tester will issue a
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# deadlock panic. We set cache_deadlock_threshold < tester_deadlock_threshold
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# to detect deadlock caused by Ruby protocol first before one caused by the
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# coalescer. Both units are in Ticks
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#
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args.cache_deadlock_threshold = 1e8
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tester_deadlock_threshold = 1e9
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# For now we're testing only GPU protocol, so we force num_cpus to be 0
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args.num_cpus = 0
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# Number of DMA engines
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n_DMAs = args.num_dmas
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# Number of CUs
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n_CUs = args.num_compute_units
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# Set test length, i.e., number of episodes per wavefront * #WFs.
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# Test length can be 1x#WFs, 10x#WFs, 100x#WFs, ...
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n_WFs = n_CUs * args.wavefronts_per_cu
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max_episodes = args.test_length * n_WFs
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# Number of SQC and Scalar caches
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assert(n_CUs % args.cu_per_sqc == 0)
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n_SQCs = n_CUs // args.cu_per_sqc
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args.num_sqc = n_SQCs
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assert(args.cu_per_scalar_cache != 0)
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n_Scalars = n_CUs // args.cu_per_scalar_cache
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args.num_scalar_cache = n_Scalars
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#
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# Create GPU Ruby random tester
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#
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tester = ProtocolTester(cus_per_sqc = args.cu_per_sqc,
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cus_per_scalar = args.cu_per_scalar_cache,
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wavefronts_per_cu = args.wavefronts_per_cu,
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workitems_per_wavefront = args.wf_size,
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num_atomic_locations = num_atomic_locs,
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num_normal_locs_per_atomic = \
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num_regular_locs_per_atomic_loc,
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max_num_episodes = max_episodes,
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episode_length = eps_length,
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debug_tester = args.debug_tester,
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random_seed = args.random_seed,
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log_file = args.log_file)
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#
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# Create a gem5 system. Note that the memory object isn't actually used by the
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# tester, but is included to ensure the gem5 memory size == Ruby memory size
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# checks. The system doesn't have real CPUs or CUs. It just has a tester that
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# has physical ports to be connected to Ruby
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#
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system = System(cpu = tester,
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mem_ranges = [AddrRange(args.mem_size)],
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cache_line_size = args.cacheline_size,
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mem_mode = 'timing')
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system.voltage_domain = VoltageDomain(voltage = args.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = args.sys_clock,
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voltage_domain = system.voltage_domain)
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#
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# Command processor is not needed for the tester since we don't run real
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# kernels. Setting it to zero disables the VIPER protocol from creating
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# a command processor and its caches.
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#
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args.num_cp = 0
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#
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# Make generic DMA sequencer for Ruby to use
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#
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dma_devices = [TesterDma()] * n_DMAs
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system.piobus = IOXBar()
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for _, dma_device in enumerate(dma_devices):
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dma_device.pio = system.piobus.mem_side_ports
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system.dma_devices = dma_devices
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#
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# Create the Ruby system
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#
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# the ruby tester reuses num_cpus to specify the
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# number of cpu ports connected to the tester object, which
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# is stored in system.cpu. because there is only ever one
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# tester object, num_cpus is not necessarily equal to the
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# size of system.cpu
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cpu_list = [ system.cpu ] * args.num_cpus
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Ruby.create_system(args, full_system = False,
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system = system, dma_ports = system.dma_devices,
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cpus = cpu_list)
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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# Assert that we got the right number of Ruby ports
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assert(len(system.ruby._cpu_ports) == n_CUs + n_SQCs + n_Scalars)
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#
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# Attach Ruby ports to the tester in the order:
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# cpu_sequencers,
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# vector_coalescers,
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# sqc_sequencers,
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# scalar_sequencers
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#
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# Note that this requires the protocol to create sequencers in this order
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#
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print("Attaching ruby ports to the tester")
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for i, ruby_port in enumerate(system.ruby._cpu_ports):
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ruby_port.no_retry_on_stall = True
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ruby_port.using_ruby_tester = True
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ruby_port.mem_request_port = system.piobus.cpu_side_ports
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if i < n_CUs:
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tester.cu_vector_ports = ruby_port.in_ports
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tester.cu_token_ports = ruby_port.gmTokenPort
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tester.max_cu_tokens = 4*n_WFs
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elif i < (n_CUs + n_SQCs):
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tester.cu_sqc_ports = ruby_port.in_ports
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else:
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tester.cu_scalar_ports = ruby_port.in_ports
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i += 1
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#
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# Attach DMA ports. Since Ruby.py doesn't return these they need to be found.
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# Connect tester's request port to each DMA sequencer's in_ports. This assumes
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# the protocol names these system.dma_cntrl<#>.
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#
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dma_ports = []
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for i in range(n_DMAs):
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dma_cntrl = getattr(system, 'dma_cntrl' + str(i))
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dma_ports.append(dma_cntrl.dma_sequencer.in_ports)
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tester.dma_ports = dma_ports
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#
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# Common variables for all types of threads
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#
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thread_clock = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.voltage_domain)
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g_thread_idx = 0
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#
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# No CPU threads are used for GPU tester
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#
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tester.cpu_threads = []
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#
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# Create DMA threads
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#
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dma_threads = []
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print("Creating %i DMAs" % n_DMAs)
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for dma_idx in range(n_DMAs):
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dma_threads.append(DmaThread(thread_id = g_thread_idx,
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num_lanes = 1, clk_domain = thread_clock,
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deadlock_threshold = \
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tester_deadlock_threshold))
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g_thread_idx += 1
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tester.dma_threads = dma_threads
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#
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# Create GPU wavefronts
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#
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wavefronts = []
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print("Creating %i WFs attached to %i CUs" % \
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(n_CUs * tester.wavefronts_per_cu, n_CUs))
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for cu_idx in range(n_CUs):
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for wf_idx in range(tester.wavefronts_per_cu):
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wavefronts.append(GpuWavefront(thread_id = g_thread_idx,
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cu_id = cu_idx,
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num_lanes = args.wf_size,
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clk_domain = thread_clock,
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deadlock_threshold = \
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tester_deadlock_threshold))
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g_thread_idx += 1
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tester.wavefronts = wavefronts
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#
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# Run simulation
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#
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root = Root(full_system = False, system = system)
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# Instantiate configuration
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m5.instantiate()
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# Simulate until tester completes
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exit_event = m5.simulate()
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print('Exiting tick: ', m5.curTick())
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print('Exiting because ', exit_event.getCause())
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