376 lines
13 KiB
C++
376 lines
13 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/fetch_seq_unit.hh"
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#include "cpu/inorder/resource_pool.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu),
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instSize(sizeof(MachInst))
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{
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for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
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delaySlotInfo[tid].numInsts = 0;
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delaySlotInfo[tid].targetReady = false;
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pcValid[tid] = false;
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pcBlockStage[tid] = 0;
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squashSeqNum[tid] = (InstSeqNum)-1;
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lastSquashCycle[tid] = 0;
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}
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}
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FetchSeqUnit::~FetchSeqUnit()
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{
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delete [] resourceEvent;
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}
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void
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FetchSeqUnit::init()
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{
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resourceEvent = new FetchSeqEvent[width];
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initSlots();
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}
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void
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FetchSeqUnit::execute(int slot_num)
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{
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// After this is working, change this to a reinterpret cast
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// for performance considerations
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ResourceRequest* fs_req = reqMap[slot_num];
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DynInstPtr inst = fs_req->inst;
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ThreadID tid = inst->readTid();
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int stage_num = fs_req->getStageNum();
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int seq_num = inst->seqNum;
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fs_req->fault = NoFault;
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switch (fs_req->cmd)
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{
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case AssignNextPC:
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{
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if (pcValid[tid]) {
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if (delaySlotInfo[tid].targetReady &&
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delaySlotInfo[tid].numInsts == 0) {
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// Set PC to target
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PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
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nextPC[tid] = PC[tid] + instSize; //next_NPC
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nextNPC[tid] = PC[tid] + (2 * instSize);
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delaySlotInfo[tid].targetReady = false;
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to delay slot target\n",tid);
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}
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inst->setPC(PC[tid]);
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inst->setNextPC(PC[tid] + instSize);
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inst->setNextNPC(PC[tid] + (instSize * 2));
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#if ISA_HAS_DELAY_SLOT
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inst->setPredTarg(inst->readNextNPC());
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#else
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inst->setPredTarg(inst->readNextPC());
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#endif
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inst->setMemAddr(PC[tid]);
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inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p, NPC %08p, NNPC %08p\n", tid,
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inst->seqNum, inst->readPC(), inst->readNextPC(), inst->readNextNPC());
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if (delaySlotInfo[tid].numInsts > 0) {
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--delaySlotInfo[tid].numInsts;
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// It's OK to set PC to target of branch
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if (delaySlotInfo[tid].numInsts == 0) {
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delaySlotInfo[tid].targetReady = true;
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}
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DPRINTF(InOrderFetchSeq, "[tid:%i]: %i delay slot inst(s) left to"
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" process.\n", tid, delaySlotInfo[tid].numInsts);
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}
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PC[tid] = nextPC[tid];
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nextPC[tid] = nextNPC[tid];
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nextNPC[tid] += instSize;
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fs_req->done();
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} else {
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DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
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fs_req->setCompleted(false);
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}
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}
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break;
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case UpdateTargetPC:
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{
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if (inst->isControl()) {
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// If it's a return, then we must wait for resolved address.
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if (inst->isReturn() && !inst->predTaken()) {
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cpu->pipelineStage[stage_num]->toPrevStages->stageBlock[stage_num][tid] = true;
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pcValid[tid] = false;
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pcBlockStage[tid] = stage_num;
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} else if (inst->isCondDelaySlot() && !inst->predTaken()) {
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// Not-Taken AND Conditional Control
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%08p] Predicted Not-Taken Cond. "
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"Delay inst. Skipping delay slot and Updating PC to %08p\n",
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tid, inst->seqNum, inst->readPC(), inst->readPredTarg());
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DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
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tid, stage_num, seq_num);
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inst->bdelaySeqNum = seq_num;
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inst->squashingStage = stage_num;
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squashAfterInst(inst, stage_num, tid);
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} else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
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// Not-Taken Control
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control "
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"inst. updating PC to %08p\n", tid, inst->seqNum,
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inst->readNextPC());
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#if ISA_HAS_DELAY_SLOT
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++delaySlotInfo[tid].numInsts;
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delaySlotInfo[tid].targetReady = false;
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delaySlotInfo[tid].targetAddr = inst->readNextNPC();
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#else
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assert(delaySlotInfo[tid].numInsts == 0);
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#endif
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} else if (inst->predTaken()) {
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// Taken Control
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#if ISA_HAS_DELAY_SLOT
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++delaySlotInfo[tid].numInsts;
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delaySlotInfo[tid].targetReady = false;
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delaySlotInfo[tid].targetAddr = inst->readPredTarg();
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay slot target "
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"to PC %08p\n", tid, inst->seqNum, inst->readPredTarg());
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inst->bdelaySeqNum = seq_num + 1;
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#else
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inst->bdelaySeqNum = seq_num;
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assert(delaySlotInfo[tid].numInsts == 0);
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#endif
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inst->squashingStage = stage_num;
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DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
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tid, stage_num, inst->bdelaySeqNum);
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// Do Squashing
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squashAfterInst(inst, stage_num, tid);
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}
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} else {
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch target update "
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"since then is not a control instruction.\n", tid, inst->seqNum);
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}
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fs_req->done();
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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}
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inline void
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FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
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{
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// Squash In Pipeline Stage
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cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
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// Squash inside current resource, so if there needs to be fetching on same cycle
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// the fetch information will be correct.
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// squash(inst, stage_num, inst->bdelaySeqNum, tid);
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// Schedule Squash Through-out Resource Pool
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cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
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}
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void
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FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
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InstSeqNum squash_seq_num, ThreadID tid)
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{
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
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tid, squash_stage);
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InstSeqNum done_seq_num = inst->bdelaySeqNum;
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Addr new_PC = inst->readPredTarg();
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if (squashSeqNum[tid] <= done_seq_num &&
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lastSquashCycle[tid] == curTick) {
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, since"
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"there is an outstanding squash that is older.\n",
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tid, squash_stage);
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} else {
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squashSeqNum[tid] = done_seq_num;
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lastSquashCycle[tid] = curTick;
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// If The very next instruction number is the done seq. num,
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// then we haven't seen the delay slot yet ... if it isn't
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// the last done_seq_num then this is the delay slot inst.
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if (cpu->nextInstSeqNum(tid) != done_seq_num &&
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!inst->procDelaySlotOnMispred) {
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delaySlotInfo[tid].numInsts = 0;
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delaySlotInfo[tid].targetReady = false;
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// Reset PC
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PC[tid] = new_PC;
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nextPC[tid] = new_PC + instSize;
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nextNPC[tid] = new_PC + (2 * instSize);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
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tid, PC[tid]);
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} else {
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#if !ISA_HAS_DELAY_SLOT
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assert(0);
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#endif
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delaySlotInfo[tid].numInsts = 1;
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delaySlotInfo[tid].targetReady = false;
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delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ? inst->branchTarget() : new_PC;
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// Reset PC to Delay Slot Instruction
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if (inst->procDelaySlotOnMispred) {
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PC[tid] = new_PC;
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nextPC[tid] = new_PC + instSize;
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nextNPC[tid] = new_PC + (2 * instSize);
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}
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}
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// Unblock Any Stages Waiting for this information to be updated ...
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if (!pcValid[tid]) {
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cpu->pipelineStage[pcBlockStage[tid]]->toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
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}
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pcValid[tid] = true;
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}
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Resource::squash(inst, squash_stage, squash_seq_num, tid);
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}
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FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
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: ResourceEvent()
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{ }
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void
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FetchSeqUnit::FetchSeqEvent::process()
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{
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FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
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assert(fs_res);
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for (int i=0; i < MaxThreads; i++) {
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fs_res->PC[i] = fs_res->cpu->readPC(i);
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fs_res->nextPC[i] = fs_res->cpu->readNextPC(i);
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fs_res->nextNPC[i] = fs_res->cpu->readNextNPC(i);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC:%08p NPC:%08p NNPC:%08p.\n",
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fs_res->PC[i], fs_res->nextPC[i], fs_res->nextNPC[i]);
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fs_res->pcValid[i] = true;
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}
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//cpu->fetchPriorityList.push_back(tid);
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}
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void
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FetchSeqUnit::activateThread(ThreadID tid)
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{
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pcValid[tid] = true;
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PC[tid] = cpu->readPC(tid);
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nextPC[tid] = cpu->readNextPC(tid);
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nextNPC[tid] = cpu->readNextNPC(tid);
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cpu->fetchPriorityList.push_back(tid);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC:%08p NPC:%08p NNPC:%08p.\n",
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tid, PC[tid], nextPC[tid], nextNPC[tid]);
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}
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void
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FetchSeqUnit::deactivateThread(ThreadID tid)
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{
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delaySlotInfo[tid].numInsts = 0;
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delaySlotInfo[tid].targetReady = false;
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pcValid[tid] = false;
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pcBlockStage[tid] = 0;
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squashSeqNum[tid] = (InstSeqNum)-1;
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lastSquashCycle[tid] = 0;
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list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
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cpu->fetchPriorityList.end(),
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tid);
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if (thread_it != cpu->fetchPriorityList.end())
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cpu->fetchPriorityList.erase(thread_it);
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}
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void
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FetchSeqUnit::suspendThread(ThreadID tid)
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{
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deactivateThread(tid);
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}
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void
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FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
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{
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pcValid[tid] = true;
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if (cpu->thread[tid]->lastGradIsBranch) {
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/** This function assumes that the instruction causing the context
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* switch was right after the branch. Thus, if it's not, then
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* we are updating incorrectly here
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*/
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assert(cpu->thread[tid]->lastBranchNextPC == inst->readPC());
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PC[tid] = cpu->thread[tid]->lastBranchNextNPC;
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nextPC[tid] = PC[tid] + instSize;
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nextNPC[tid] = nextPC[tid] + instSize;
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} else {
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PC[tid] = inst->readNextPC();
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nextPC[tid] = inst->readNextNPC();
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nextNPC[tid] = inst->readNextNPC() + instSize;
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}
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
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"Assigning PC:%08p NPC:%08p NNPC:%08p.\n", tid, PC[tid],
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nextPC[tid], nextNPC[tid]);
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}
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