60 lines
1.7 KiB
Python
60 lines
1.7 KiB
Python
from gem5.isas import ISA
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from m5.objects import (
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ArmDefaultRelease,
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)
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from gem5.utils.requires import requires
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from gem5.resources.workload import CustomWorkload
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from gem5.resources.resource import BinaryResource
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from gem5.simulate.simulator import Simulator
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from m5.objects import VExpress_GEM5_Foundation
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from gem5.components.boards.arm_baremetal_board import ArmBareMetalBoard
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from gem5.components.memory import DRAMSysHBM2
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.components.processors.simple_processor import SimpleProcessor
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requires(isa_required=ISA.ARM)
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from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
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PrivateL1PrivateL2CacheHierarchy,
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)
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from gem5.components.cachehierarchies.classic.no_cache import NoCache
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cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
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l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
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)
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# cache_hierarchy = NoCache()
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memory = DRAMSysHBM2(recordable=True)
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processor = SimpleProcessor(cpu_type=CPUTypes.O3, num_cores=1, isa=ISA.ARM)
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release = ArmDefaultRelease()
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platform = VExpress_GEM5_Foundation()
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board = ArmBareMetalBoard(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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release=release,
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platform=platform,
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)
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# HBM2 requires line size of 32 Bytes
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board.cache_line_size = 32
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for core in processor.get_cores():
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core.core.fetchBufferSize = 32
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# Address of memory-mapped m5ops
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board.m5ops_base = 0x10010000
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workload = CustomWorkload(
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"set_baremetal_workload",
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{
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"kernel": BinaryResource("pim-os"),
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},
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)
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board.set_workload(workload)
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simulator = Simulator(board=board)
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simulator.run()
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