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f1dce36f97dc1290e622884eaf81bf28aca49e0e
gem5/src/dev
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Giacomo Travaglini f1dce36f97 arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer 
Change-Id: I0cc499e1309c35d946c5b9231846263f97bfa2b0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58110
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-24 16:04:58 +00:00
..
amdgpu
dev-amdgpu: Add checkpoint support to AMDGPUDevice
2022-03-24 14:59:57 +00:00
arm
arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer
2022-03-24 16:04:58 +00:00
hsa
dev-hsa: Update HSA queue tracking for FS mode
2022-03-17 14:35:35 +00:00
i2c
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
lupio
dev: Remove unused private variable in lupio_tmr.hh
2021-12-09 00:39:10 +00:00
mips
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
net
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
pci
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
ps2
dev: Implement PS/2 keyboard echo and set scan code commands.
2022-03-15 06:54:31 +00:00
qemu
dev: Add a qemu fw config item for a byte array.
2022-03-14 03:20:47 +00:00
riscv
arch-riscv, dev: add VirtIO entropy device(VirtIORng) support
2022-01-21 01:18:31 +00:00
serial
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
sparc
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
storage
dev: Don't implement the ATAPI_IDENTIFY_DEVICE command.
2022-02-26 01:59:13 +00:00
virtio
dev: Make VirtIORng device use gem5's rng instead of C++'s
2022-02-23 02:21:15 +00:00
x86
dev,arch-x86: Implement some self test 8042 commands.
2022-03-14 16:53:14 +00:00
baddev.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
baddev.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
BadDevice.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Device.py
dev,dev-hsa,gpu-compute: Refactor dmaVirt calls
2021-07-09 22:40:18 +00:00
dma_device.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dma_device.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dma_virt_device.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
dma_virt_device.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
intel_8254_timer.cc
dev: Refactor how counters are set up in the 8254 timer.
2022-01-16 03:43:58 +00:00
intel_8254_timer.hh
dev: Refactor how counters are set up in the 8254 timer.
2022-01-16 03:43:58 +00:00
intpin.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
intpin.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
IntPin.py
dev: define VectorIntSourcePin type
2022-01-12 01:48:19 +00:00
io_device.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
io_device.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_fake.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_fake.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mc146818.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mc146818.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pixelpump.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pixelpump.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
platform.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
platform.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Platform.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_bank.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
reg_bank.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
rtcreg.h
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
SConscript
scons: Make the sim_objects parameter of SimObject mandantory.
2021-12-15 10:48:03 +00:00