Andreas Hansson aab2001ab7 Python: Make the All proxy traverse SimObject children as well ...

This patch changes the behaviour of the All proxy parameter to not
only consider the direct children, but also do a pre-order depth-first
traversal of the object tree and append all results from the
children.

This is used in a later patch to find all the memories in the system,
independent of where they are located in the hierarchy.

2012-04-05 10:44:35 -04:00

..

arch

X86: Fix address size handling so real mode works properly.

2012-03-31 12:27:33 -07:00

base

range_map: Enable const find and iteration

2012-03-26 05:37:00 -04:00

cpu

Atomic: Remove the physmem_port and access memory directly

2012-04-03 03:50:14 -04:00

dev

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

doxygen

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kern

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem

MEM: Remove legacy DRAM in preparation for memory updates

2012-03-30 12:57:48 -04:00

python

Python: Make the All proxy traverse SimObject children as well

2012-04-05 10:44:35 -04:00

sim

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

unittest

Stats: Add a sparse histogram stat object.

2011-08-19 15:08:05 -05:00

Doxyfile

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SConscript

Scons: Remove Werror=False in SConscript files

2012-03-22 06:34:50 -04:00