Giacomo Travaglini 27378ecbe4 Revert "cpu: fix how a thread starts up in MinorCPU" ...

This reverts commit 02dafc5498.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I0a8098fc71abe5838014e587dbe372b258d8aa9f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18604
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-05-14 08:44:37 +00:00

..

arch

arch-arm: Add initial support for SVE contiguous loads/stores

2019-05-11 12:49:15 +00:00

base

base: Add operators to SatCounter

2019-05-14 07:55:06 +00:00

cpu

Revert "cpu: fix how a thread starts up in MinorCPU"

2019-05-14 08:44:37 +00:00

dev

dev: StreamID generation in DMA device

2019-05-03 08:38:12 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

…

gpu-compute

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

kern

arch: cpu: Track kernel stats using the base ISA agnostic type.

2019-04-30 03:49:40 +00:00

learning_gem5

learning_gem5: Fix vector port panic in SimpleCache

2019-04-08 22:51:38 +00:00

mem

mem-cache: Use SatCounter for prefetchers

2019-05-14 07:55:06 +00:00

proto

…

python

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

sim

sim-se: correct statfs inclusion on !linux host

2019-05-06 18:20:44 +00:00

systemc

systemc: Add a distinct async_request_update mechanism.

2019-04-30 01:27:45 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: fix disable_partial logic for fast binary

2019-03-18 22:22:25 +00:00