Ronald Dreslinski 38ee552798 configs: actually add ARMv7a-like cpu/cache file

2012-01-26 16:44:43 -05:00

..

Benchmarks.py

ARM: Update config files for Android/BBench images available on website.

2011-12-15 00:43:35 -05:00

CacheConfig.py

configs: A more realistic configuration of an ARM-like processor

2012-01-26 14:53:48 -05:00

Caches.py

O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

2011-12-01 00:15:22 -08:00

cpu2000.py

cpu2000: Add missing art benchmark to all

2012-01-09 18:08:20 -06:00

FSConfig.py

MEM: Removing the default port peer from Python ports

2012-01-17 12:55:09 -06:00

O3_ARM_v7a.py

configs: actually add ARMv7a-like cpu/cache file

2012-01-26 16:44:43 -05:00

Options.py

configs: A more realistic configuration of an ARM-like processor

2012-01-26 14:53:48 -05:00

Simulation.py

configs: A more realistic configuration of an ARM-like processor

2012-01-26 14:53:48 -05:00

SysPaths.py

make rcS files read from the m5 source directory, not /dist.

2006-11-08 14:10:25 -05:00