fcb544d569
We are allowing the L2 TLB to store partial translations from the second level of lookup JIRA: https://gem5.atlassian.net/browse/GEM5-1108 Change-Id: I1286c14a256470c2075fe5533930617139d4d087 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52126 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
107 lines
4.4 KiB
Python
107 lines
4.4 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2020-2021 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.ArmSystem import ArmRelease
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from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB
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from m5.objects.BaseMMU import BaseMMU
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from m5.objects.ClockedObject import ClockedObject
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from m5.params import *
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from m5.proxy import *
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# Basic stage 1 translation objects
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class ArmTableWalker(ClockedObject):
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type = 'ArmTableWalker'
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cxx_class = 'gem5::ArmISA::TableWalker'
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cxx_header = "arch/arm/table_walker.hh"
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is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
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num_squash_per_cycle = Param.Unsigned(2,
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"Number of outstanding walks that can be squashed per cycle")
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port = RequestPort("Table Walker port")
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sys = Param.System(Parent.any, "system object parameter")
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# Stage 2 translation objects, only used when virtualisation is being used
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class ArmStage2TableWalker(ArmTableWalker):
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is_stage2 = True
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class ArmMMU(BaseMMU):
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type = 'ArmMMU'
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cxx_class = 'gem5::ArmISA::MMU'
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cxx_header = 'arch/arm/mmu.hh'
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# L2 TLBs
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l2_shared = ArmTLB(entry_type="unified", size=1280,
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partial_levels=["L2"])
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# L1 TLBs
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itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)
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dtb = ArmTLB(entry_type="data", next_level=Parent.l2_shared)
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stage2_itb = Param.ArmTLB(
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ArmStage2TLB(entry_type="instruction"),
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"Stage 2 Instruction TLB")
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stage2_dtb = Param.ArmTLB(
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ArmStage2TLB(entry_type="data"),
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"Stage 2 Data TLB")
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itb_walker = Param.ArmTableWalker(
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ArmTableWalker(), "HW Table walker")
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dtb_walker = Param.ArmTableWalker(
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ArmTableWalker(), "HW Table walker")
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stage2_itb_walker = Param.ArmTableWalker(
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ArmStage2TableWalker(), "HW Table walker")
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stage2_dtb_walker = Param.ArmTableWalker(
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ArmStage2TableWalker(), "HW Table walker")
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sys = Param.System(Parent.any, "system object parameter")
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release_se = Param.ArmRelease(Parent.isa[0].release_se,
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"Set of features/extensions to use in SE mode")
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@classmethod
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def walkerPorts(cls):
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return ["mmu.itb_walker.port", "mmu.dtb_walker.port",
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"mmu.stage2_itb_walker.port", "mmu.stage2_dtb_walker.port"]
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def connectWalkerPorts(self, iport, dport):
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self.itb_walker.port = iport
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self.dtb_walker.port = dport
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self.stage2_itb_walker.port = iport
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self.stage2_dtb_walker.port = dport
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