75c281114a
Rename m5op C symbols to be prefixed all lower case, separated by underscore, and prefixed by m5. This avoids potential name clashes for short names such as arm. Change-Id: Ic42f94d8a722661ef96c151d627e31eeb2e51490 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jose Marinho <jose.marinho@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4264 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
134 lines
5.2 KiB
ArmAsm
134 lines
5.2 KiB
ArmAsm
/*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Ali Saidi
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*/
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#define m5_op 0x01
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#include <gem5/asm/generic/m5ops.h>
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#define INST(op, ra, rb, func) \
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.long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
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#define LEAF(func) \
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.align 3; \
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.globl func; \
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.ent func; \
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func:
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#define RET \
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ret ($26)
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#define END(func) \
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.end func
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#define SIMPLE_OP(_f, _o) \
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LEAF(_f) \
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_o; \
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RET; \
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END(_f)
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#define ARM(reg) INST(m5_op, reg, 0, M5OP_ARM)
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#define QUIESCE INST(m5_op, 0, 0, M5OP_QUIESCE)
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#define QUIESCENS(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_NS)
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#define QUIESCECYC(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_CYCLE)
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#define QUIESCETIME INST(m5_op, 0, 0, M5OP_QUIESCE_TIME)
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#define RPNS INST(m5_op, 0, 0, M5OP_RPNS)
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#define WAKE_CPU(r1) INST(m5_op, r1, 0, M5OP_WAKE_CPU)
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#define M5EXIT(reg) INST(m5_op, reg, 0, M5OP_EXIT)
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#define INITPARAM(reg) INST(m5_op, reg, 0, M5OP_INIT_PARAM)
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#define LOADSYMBOL(reg) INST(m5_op, reg, 0, M5OP_LOAD_SYMBOL)
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#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_RESET_STATS)
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#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_STATS)
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#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_RESET_STATS)
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#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, M5OP_CHECKPOINT)
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#define READFILE INST(m5_op, 0, 0, M5OP_READ_FILE)
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#define DEBUGBREAK INST(m5_op, 0, 0, M5OP_DEBUG_BREAK)
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#define SWITCHCPU INST(m5_op, 0, 0, M5OP_SWITCH_CPU)
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#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, M5OP_ADD_SYMBOL)
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#define PANIC INST(m5_op, 0, 0, M5OP_PANIC)
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#define AN_BSM INST(m5_op, M5OP_AN_BSM, 0, M5OP_ANNOTATE)
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#define AN_ESM INST(m5_op, M5OP_AN_ESM, 0, M5OP_ANNOTATE)
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#define AN_BEGIN INST(m5_op, M5OP_AN_BEGIN, 0, M5OP_ANNOTATE)
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#define AN_END INST(m5_op, M5OP_AN_END, 0, M5OP_ANNOTATE)
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#define AN_Q INST(m5_op, M5OP_AN_Q, 0, M5OP_ANNOTATE)
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#define AN_RQ INST(m5_op, M5OP_AN_RQ, 0, M5OP_ANNOTATE)
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#define AN_DQ INST(m5_op, M5OP_AN_DQ, 0, M5OP_ANNOTATE)
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#define AN_WF INST(m5_op, M5OP_AN_WF, 0, M5OP_ANNOTATE)
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#define AN_WE INST(m5_op, M5OP_AN_WE, 0, M5OP_ANNOTATE)
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#define AN_WS INST(m5_op, M5OP_AN_WS, 0, M5OP_ANNOTATE)
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#define AN_SQ INST(m5_op, M5OP_AN_SQ, 0, M5OP_ANNOTATE)
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#define AN_AQ INST(m5_op, M5OP_AN_AQ, 0, M5OP_ANNOTATE)
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#define AN_PQ INST(m5_op, M5OP_AN_PQ, 0, M5OP_ANNOTATE)
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#define AN_L INST(m5_op, M5OP_AN_L, 0, M5OP_ANNOTATE)
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#define AN_IDENTIFY INST(m5_op, M5OP_AN_IDENTIFY, 0, M5OP_ANNOTATE)
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#define AN_GETID INST(m5_op, M5OP_AN_GETID, 0, M5OP_ANNOTATE)
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.set noreorder
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SIMPLE_OP(m5_arm, ARM(16))
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SIMPLE_OP(m5_quiesce, QUIESCE)
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SIMPLE_OP(m5_quiesce_ns, QUIESCENS(16))
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SIMPLE_OP(m5_quiesce_cycle, QUIESCECYC(16))
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SIMPLE_OP(m5_quiesce_time, QUIESCETIME)
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SIMPLE_OP(m5_rpns, RPNS)
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SIMPLE_OP(m5_wake_cpu, WAKE_CPU(16))
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SIMPLE_OP(m5_exit, M5EXIT(16))
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SIMPLE_OP(m5_init_param, INITPARAM(0))
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SIMPLE_OP(m5_load_symbol, LOADSYMBOL(0))
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SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17))
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SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17))
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SIMPLE_OP(m5_dump_reset_stats, DUMPRST_STATS(16, 17))
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SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17))
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SIMPLE_OP(m5_read_file, READFILE)
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SIMPLE_OP(m5_debug_break, DEBUGBREAK)
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SIMPLE_OP(m5_switch_cpu, SWITCHCPU)
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SIMPLE_OP(m5_add_symbol, ADDSYMBOL(16, 17))
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SIMPLE_OP(m5_panic, PANIC)
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SIMPLE_OP(m5a_bsm, AN_BSM)
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SIMPLE_OP(m5a_esm, AN_ESM)
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SIMPLE_OP(m5a_begin, AN_BEGIN)
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SIMPLE_OP(m5a_end, AN_END)
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SIMPLE_OP(m5a_q, AN_Q)
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SIMPLE_OP(m5a_rq, AN_RQ)
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SIMPLE_OP(m5a_dq, AN_DQ)
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SIMPLE_OP(m5a_wf, AN_WF)
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SIMPLE_OP(m5a_we, AN_WE)
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SIMPLE_OP(m5a_ws, AN_WS)
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SIMPLE_OP(m5a_sq, AN_SQ)
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SIMPLE_OP(m5a_aq, AN_AQ)
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SIMPLE_OP(m5a_pq, AN_PQ)
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SIMPLE_OP(m5a_l, AN_L)
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SIMPLE_OP(m5a_identify, AN_IDENTIFY)
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SIMPLE_OP(m5a_getid, AN_GETID)
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