ed3e52663b
Change-Id: Ie84a29e779187effea372c6289688f32a1db075d Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36635 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
111 lines
5.0 KiB
Python
111 lines
5.0 KiB
Python
# Copyright (c) 2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# Copyright (c) 2020 ARM Limited
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.ClockedObject import ClockedObject
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class RubyPort(ClockedObject):
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type = 'RubyPort'
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abstract = True
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cxx_header = "mem/ruby/system/RubyPort.hh"
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version = Param.Int(0, "")
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in_ports = VectorResponsePort("CPU side of this RubyPort/Sequencer. "
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"The CPU request ports should be connected to this. If a CPU "
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"has multiple ports (e.g., I/D ports) all of the ports for a "
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"single CPU can connect to one RubyPort.")
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slave = DeprecatedParam(in_ports,
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'`slave` is now called `in_ports`')
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interrupt_out_port = VectorRequestPort("Port to connect to x86 interrupt "
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"controller to send the CPU requests from outside.")
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master = DeprecatedParam(interrupt_out_port,
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'`master` is now called `interrupt_out_port`')
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pio_request_port = RequestPort("Ruby pio request port")
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pio_master_port = DeprecatedParam(pio_request_port,
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'`pio_master_port` is now called `pio_request_port`')
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mem_request_port = RequestPort("Ruby mem request port")
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mem_master_port = DeprecatedParam(mem_request_port,
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'`mem_master_port` is now called `mem_request_port`')
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pio_response_port = ResponsePort("Ruby pio response port")
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pio_slave_port = DeprecatedParam(pio_response_port,
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'`pio_slave_port` is now called `pio_response_port`')
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using_ruby_tester = Param.Bool(False, "")
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no_retry_on_stall = Param.Bool(False, "")
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ruby_system = Param.RubySystem(Parent.any, "")
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system = Param.System(Parent.any, "system object")
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support_data_reqs = Param.Bool(True, "data cache requests supported")
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support_inst_reqs = Param.Bool(True, "inst cache requests supported")
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is_cpu_sequencer = Param.Bool(True, "connected to a cpu")
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class RubyPortProxy(RubyPort):
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type = 'RubyPortProxy'
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cxx_header = "mem/ruby/system/RubyPortProxy.hh"
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class RubySequencer(RubyPort):
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type = 'RubySequencer'
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cxx_class = 'Sequencer'
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cxx_header = "mem/ruby/system/Sequencer.hh"
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dcache = Param.RubyCache("")
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max_outstanding_requests = Param.Int(16,
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"max requests (incl. prefetches) outstanding")
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deadlock_threshold = Param.Cycles(500000,
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"max outstanding cycles for a request before deadlock/livelock declared")
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garnet_standalone = Param.Bool(False, "")
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# id used by protocols that support multiple sequencers per controller
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# 99 is the dummy default value
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coreid = Param.Int(99, "CorePair core id")
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class RubyHTMSequencer(RubySequencer):
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type = 'RubyHTMSequencer'
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cxx_class = 'HTMSequencer'
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cxx_header = "mem/ruby/system/HTMSequencer.hh"
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class DMASequencer(RubyPort):
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type = 'DMASequencer'
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cxx_header = "mem/ruby/system/DMASequencer.hh"
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max_outstanding_requests = Param.Int(64, "max outstanding requests")
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