arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
213 lines
6.8 KiB
C++
213 lines
6.8 KiB
C++
/*
|
|
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#ifndef __PROCESS_HH__
|
|
#define __PROCESS_HH__
|
|
|
|
//
|
|
// The purpose of this code is to fake the loader & syscall mechanism
|
|
// when there's no OS: thus there's no reason to use it in FULL_SYSTEM
|
|
// mode when we do have an OS.
|
|
//
|
|
#include "config/full_system.hh"
|
|
|
|
#if !FULL_SYSTEM
|
|
|
|
#include <vector>
|
|
|
|
#include "arch/isa_traits.hh"
|
|
#include "sim/sim_object.hh"
|
|
#include "sim/stats.hh"
|
|
#include "base/statistics.hh"
|
|
#include "base/trace.hh"
|
|
|
|
class ExecContext;
|
|
class FunctionalMemory;
|
|
class Process : public SimObject
|
|
{
|
|
protected:
|
|
typedef TheISA::Addr Addr;
|
|
typedef TheISA::RegFile RegFile;
|
|
typedef TheISA::MachInst MachInst;
|
|
public:
|
|
|
|
// have we initialized an execution context from this process? If
|
|
// yes, subsequent contexts are assumed to be for dynamically
|
|
// created threads and are not initialized.
|
|
bool initialContextLoaded;
|
|
|
|
// execution contexts associated with this process
|
|
std::vector<ExecContext *> execContexts;
|
|
|
|
// number of CPUs (esxec contexts, really) assigned to this process.
|
|
unsigned int numCpus() { return execContexts.size(); }
|
|
|
|
// record of blocked context
|
|
struct WaitRec
|
|
{
|
|
Addr waitChan;
|
|
ExecContext *waitingContext;
|
|
|
|
WaitRec(Addr chan, ExecContext *ctx)
|
|
: waitChan(chan), waitingContext(ctx)
|
|
{
|
|
}
|
|
};
|
|
|
|
// list of all blocked contexts
|
|
std::list<WaitRec> waitList;
|
|
|
|
RegFile *init_regs; // initial register contents
|
|
|
|
Addr text_base; // text (code) segment base
|
|
unsigned text_size; // text (code) size in bytes
|
|
|
|
Addr data_base; // initialized data segment base
|
|
unsigned data_size; // initialized data + bss size in bytes
|
|
|
|
Addr brk_point; // top of the data segment
|
|
|
|
Addr stack_base; // stack segment base (highest address)
|
|
unsigned stack_size; // initial stack size
|
|
Addr stack_min; // lowest address accessed on the stack
|
|
|
|
// addr to use for next stack region (for multithreaded apps)
|
|
Addr next_thread_stack_base;
|
|
|
|
// Base of region for mmaps (when user doesn't specify an address).
|
|
Addr mmap_start;
|
|
Addr mmap_end;
|
|
|
|
// Base of region for nxm data
|
|
Addr nxm_start;
|
|
Addr nxm_end;
|
|
|
|
std::string prog_fname; // file name
|
|
Addr prog_entry; // entry point (initial PC)
|
|
|
|
Stats::Scalar<> num_syscalls; // number of syscalls executed
|
|
|
|
|
|
protected:
|
|
// constructor
|
|
Process(const std::string &nm,
|
|
int stdin_fd, // initial I/O descriptors
|
|
int stdout_fd,
|
|
int stderr_fd);
|
|
|
|
// post initialization startup
|
|
virtual void startup();
|
|
|
|
protected:
|
|
FunctionalMemory *memory;
|
|
|
|
private:
|
|
// file descriptor remapping support
|
|
static const int MAX_FD = 256; // max legal fd value
|
|
int fd_map[MAX_FD+1];
|
|
|
|
public:
|
|
// static helper functions to generate file descriptors for constructor
|
|
static int openInputFile(const std::string &filename);
|
|
static int openOutputFile(const std::string &filename);
|
|
|
|
// override of virtual SimObject method: register statistics
|
|
virtual void regStats();
|
|
|
|
// register an execution context for this process.
|
|
// returns xc's cpu number (index into execContexts[])
|
|
int registerExecContext(ExecContext *xc);
|
|
|
|
|
|
void replaceExecContext(ExecContext *xc, int xcIndex);
|
|
|
|
// map simulator fd sim_fd to target fd tgt_fd
|
|
void dup_fd(int sim_fd, int tgt_fd);
|
|
|
|
// generate new target fd for sim_fd
|
|
int alloc_fd(int sim_fd);
|
|
|
|
// free target fd (e.g., after close)
|
|
void free_fd(int tgt_fd);
|
|
|
|
// look up simulator fd for given target fd
|
|
int sim_fd(int tgt_fd);
|
|
|
|
// is this a valid instruction fetch address?
|
|
bool validInstAddr(Addr addr)
|
|
{
|
|
return (text_base <= addr &&
|
|
addr < text_base + text_size &&
|
|
!(addr & (sizeof(MachInst)-1)));
|
|
}
|
|
|
|
// is this a valid address? (used to filter data fetches)
|
|
// note that we just assume stack size <= 16MB
|
|
// this may be alpha-specific
|
|
bool validDataAddr(Addr addr)
|
|
{
|
|
return ((data_base <= addr && addr < brk_point) ||
|
|
(next_thread_stack_base <= addr && addr < stack_base) ||
|
|
(text_base <= addr && addr < (text_base + text_size)) ||
|
|
(mmap_start <= addr && addr < mmap_end) ||
|
|
(nxm_start <= addr && addr < nxm_end));
|
|
}
|
|
|
|
virtual void syscall(ExecContext *xc) = 0;
|
|
|
|
virtual FunctionalMemory *getMemory() { return memory; }
|
|
};
|
|
|
|
//
|
|
// "Live" process with system calls redirected to host system
|
|
//
|
|
class ObjectFile;
|
|
class LiveProcess : public Process
|
|
{
|
|
protected:
|
|
LiveProcess(const std::string &nm, ObjectFile *objFile,
|
|
int stdin_fd, int stdout_fd, int stderr_fd,
|
|
std::vector<std::string> &argv,
|
|
std::vector<std::string> &envp);
|
|
|
|
public:
|
|
// this function is used to create the LiveProcess object, since
|
|
// we can't tell which subclass of LiveProcess to use until we
|
|
// open and look at the object file.
|
|
static LiveProcess *create(const std::string &nm,
|
|
int stdin_fd, int stdout_fd, int stderr_fd,
|
|
std::string executable,
|
|
std::vector<std::string> &argv,
|
|
std::vector<std::string> &envp);
|
|
};
|
|
|
|
|
|
#endif // !FULL_SYSTEM
|
|
|
|
#endif // __PROCESS_HH__
|