eacc352ebd
This struct is now empty, although we still need to keep it until all the types within O3 have been de-templated and no longer need a template argument. Change-Id: I3889bdbb1b8d638f7b04e5bfb7698e35eb7f2e57 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42103 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
627 lines
20 KiB
C++
627 lines
20 KiB
C++
/*
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* Copyright (c) 2012-2014,2017-2018,2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_LSQ_UNIT_HH__
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#define __CPU_O3_LSQ_UNIT_HH__
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#include <algorithm>
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#include <cstring>
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#include <map>
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#include <memory>
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#include <queue>
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#include "arch/generic/debugfaults.hh"
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#include "arch/generic/vec_reg.hh"
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#include "arch/locked_mem.hh"
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#include "config/the_isa.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/dyn_inst_ptr.hh"
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#include "cpu/o3/lsq.hh"
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#include "cpu/timebuf.hh"
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#include "debug/HtmCpu.hh"
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#include "debug/LSQUnit.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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struct DerivO3CPUParams;
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#include "base/circular_queue.hh"
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template <class Impl>
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class DefaultIEW;
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/**
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* Class that implements the actual LQ and SQ for each specific
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* thread. Both are circular queues; load entries are freed upon
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* committing, while store entries are freed once they writeback. The
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* LSQUnit tracks if there are memory ordering violations, and also
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* detects partial load to store forwarding cases (a store only has
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* part of a load's data) that requires the load to wait until the
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* store writes back. In the former case it holds onto the instruction
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* until the dependence unit looks at it, and in the latter it stalls
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* the LSQ until the store writes back. At that point the load is
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* replayed.
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*/
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template <class Impl>
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class LSQUnit
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{
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public:
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static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
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using LSQSenderState = typename LSQ<Impl>::LSQSenderState;
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using LSQRequest = typename LSQ<Impl>::LSQRequest;
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private:
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class LSQEntry
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{
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private:
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/** The instruction. */
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O3DynInstPtr inst;
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/** The request. */
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LSQRequest* req = nullptr;
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/** The size of the operation. */
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uint32_t _size = 0;
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/** Valid entry. */
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bool _valid = false;
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public:
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~LSQEntry()
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{
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if (req != nullptr) {
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req->freeLSQEntry();
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req = nullptr;
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}
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}
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void
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clear()
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{
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inst = nullptr;
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if (req != nullptr) {
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req->freeLSQEntry();
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}
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req = nullptr;
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_valid = false;
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_size = 0;
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}
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void
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set(const O3DynInstPtr& inst)
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{
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assert(!_valid);
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this->inst = inst;
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_valid = true;
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_size = 0;
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}
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LSQRequest* request() { return req; }
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void setRequest(LSQRequest* r) { req = r; }
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bool hasRequest() { return req != nullptr; }
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/** Member accessors. */
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/** @{ */
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bool valid() const { return _valid; }
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uint32_t& size() { return _size; }
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const uint32_t& size() const { return _size; }
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const O3DynInstPtr& instruction() const { return inst; }
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/** @} */
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};
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class SQEntry : public LSQEntry
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{
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private:
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/** The store data. */
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char _data[MaxDataBytes];
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/** Whether or not the store can writeback. */
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bool _canWB = false;
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/** Whether or not the store is committed. */
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bool _committed = false;
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/** Whether or not the store is completed. */
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bool _completed = false;
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/** Does this request write all zeros and thus doesn't
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* have any data attached to it. Used for cache block zero
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* style instructs (ARM DC ZVA; ALPHA WH64)
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*/
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bool _isAllZeros = false;
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public:
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static constexpr size_t DataSize = sizeof(_data);
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/** Constructs an empty store queue entry. */
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SQEntry()
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{
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std::memset(_data, 0, DataSize);
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}
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void
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set(const O3DynInstPtr& inst)
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{
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LSQEntry::set(inst);
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}
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void
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clear()
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{
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LSQEntry::clear();
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_canWB = _completed = _committed = _isAllZeros = false;
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}
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/** Member accessors. */
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/** @{ */
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bool& canWB() { return _canWB; }
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const bool& canWB() const { return _canWB; }
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bool& completed() { return _completed; }
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const bool& completed() const { return _completed; }
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bool& committed() { return _committed; }
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const bool& committed() const { return _committed; }
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bool& isAllZeros() { return _isAllZeros; }
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const bool& isAllZeros() const { return _isAllZeros; }
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char* data() { return _data; }
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const char* data() const { return _data; }
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/** @} */
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};
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using LQEntry = LSQEntry;
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/** Coverage of one address range with another */
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enum class AddrRangeCoverage
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{
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PartialAddrRangeCoverage, /* Two ranges partly overlap */
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FullAddrRangeCoverage, /* One range fully covers another */
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NoAddrRangeCoverage /* Two ranges are disjoint */
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};
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public:
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using LoadQueue = CircularQueue<LQEntry>;
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using StoreQueue = CircularQueue<SQEntry>;
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public:
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/** Constructs an LSQ unit. init() must be called prior to use. */
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LSQUnit(uint32_t lqEntries, uint32_t sqEntries);
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/** We cannot copy LSQUnit because it has stats for which copy
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* contructor is deleted explicitly. However, STL vector requires
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* a valid copy constructor for the base type at compile time.
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*/
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LSQUnit(const LSQUnit &l): stats(nullptr)
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{
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panic("LSQUnit is not copy-able");
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}
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/** Initializes the LSQ unit with the specified number of entries. */
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void init(FullO3CPU<Impl> *cpu_ptr, DefaultIEW<Impl> *iew_ptr,
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const DerivO3CPUParams ¶ms, LSQ<Impl> *lsq_ptr, unsigned id);
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/** Returns the name of the LSQ unit. */
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std::string name() const;
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/** Sets the pointer to the dcache port. */
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void setDcachePort(RequestPort *dcache_port);
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/** Perform sanity checks after a drain. */
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void drainSanityCheck() const;
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Inserts an instruction. */
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void insert(const O3DynInstPtr &inst);
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/** Inserts a load instruction. */
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void insertLoad(const O3DynInstPtr &load_inst);
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/** Inserts a store instruction. */
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void insertStore(const O3DynInstPtr &store_inst);
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/** Check for ordering violations in the LSQ. For a store squash if we
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* ever find a conflicting load. For a load, only squash if we
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* an external snoop invalidate has been seen for that load address
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* @param load_idx index to start checking at
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* @param inst the instruction to check
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*/
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Fault checkViolations(typename LoadQueue::iterator& loadIt,
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const O3DynInstPtr& inst);
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/** Check if an incoming invalidate hits in the lsq on a load
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* that might have issued out of order wrt another load beacuse
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* of the intermediate invalidate.
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*/
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void checkSnoop(PacketPtr pkt);
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/** Executes a load instruction. */
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Fault executeLoad(const O3DynInstPtr &inst);
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Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
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/** Executes a store instruction. */
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Fault executeStore(const O3DynInstPtr &inst);
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/** Commits the head load. */
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void commitLoad();
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/** Commits loads older than a specific sequence number. */
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void commitLoads(InstSeqNum &youngest_inst);
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/** Commits stores older than a specific sequence number. */
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void commitStores(InstSeqNum &youngest_inst);
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/** Writes back stores. */
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void writebackStores();
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/** Completes the data access that has been returned from the
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* memory system. */
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void completeDataAccess(PacketPtr pkt);
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/** Squashes all instructions younger than a specific sequence number. */
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void squash(const InstSeqNum &squashed_num);
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/** Returns if there is a memory ordering violation. Value is reset upon
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* call to getMemDepViolator().
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*/
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bool violation() { return memDepViolator; }
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/** Returns the memory ordering violator. */
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O3DynInstPtr getMemDepViolator();
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/** Returns the number of free LQ entries. */
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unsigned numFreeLoadEntries();
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/** Returns the number of free SQ entries. */
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unsigned numFreeStoreEntries();
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/** Returns the number of loads in the LQ. */
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int numLoads() { return loads; }
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/** Returns the number of stores in the SQ. */
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int numStores() { return stores; }
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// hardware transactional memory
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int numHtmStarts() const { return htmStarts; }
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int numHtmStops() const { return htmStops; }
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void resetHtmStartsStops() { htmStarts = htmStops = 0; }
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uint64_t getLatestHtmUid() const
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{
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const auto& htm_cpt = cpu->tcBase(lsqID)->getHtmCheckpointPtr();
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return htm_cpt->getHtmUid();
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}
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void setLastRetiredHtmUid(uint64_t htm_uid)
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{
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assert(htm_uid >= lastRetiredHtmUid);
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lastRetiredHtmUid = htm_uid;
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}
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/** Returns if either the LQ or SQ is full. */
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bool isFull() { return lqFull() || sqFull(); }
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/** Returns if both the LQ and SQ are empty. */
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bool isEmpty() const { return lqEmpty() && sqEmpty(); }
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/** Returns if the LQ is full. */
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bool lqFull() { return loadQueue.full(); }
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/** Returns if the SQ is full. */
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bool sqFull() { return storeQueue.full(); }
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/** Returns if the LQ is empty. */
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bool lqEmpty() const { return loads == 0; }
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/** Returns if the SQ is empty. */
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bool sqEmpty() const { return stores == 0; }
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/** Returns the number of instructions in the LSQ. */
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unsigned getCount() { return loads + stores; }
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/** Returns if there are any stores to writeback. */
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bool hasStoresToWB() { return storesToWB; }
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/** Returns the number of stores to writeback. */
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int numStoresToWB() { return storesToWB; }
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/** Returns if the LSQ unit will writeback on this cycle. */
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bool
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willWB()
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{
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return storeWBIt.dereferenceable() &&
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storeWBIt->valid() &&
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storeWBIt->canWB() &&
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!storeWBIt->completed() &&
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!isStoreBlocked;
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}
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/** Handles doing the retry. */
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void recvRetry();
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unsigned int cacheLineSize();
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private:
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/** Reset the LSQ state */
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void resetState();
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/** Writes back the instruction, sending it to IEW. */
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void writeback(const O3DynInstPtr &inst, PacketPtr pkt);
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/** Try to finish a previously blocked write back attempt */
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void writebackBlockedStore();
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/** Completes the store at the specified index. */
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void completeStore(typename StoreQueue::iterator store_idx);
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/** Handles completing the send of a store to memory. */
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void storePostSend();
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public:
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/** Attempts to send a packet to the cache.
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* Check if there are ports available. Return true if
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* there are, false if there are not.
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*/
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bool trySendPacket(bool isLoad, PacketPtr data_pkt);
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/** Debugging function to dump instructions in the LSQ. */
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void dumpInsts() const;
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/** Schedule event for the cpu. */
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void schedule(Event& ev, Tick when) { cpu->schedule(ev, when); }
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BaseMMU* getMMUPtr() { return cpu->mmu; }
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private:
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/** Pointer to the CPU. */
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FullO3CPU<Impl> *cpu;
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/** Pointer to the IEW stage. */
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DefaultIEW<Impl> *iewStage;
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/** Pointer to the LSQ. */
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LSQ<Impl> *lsq;
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/** Pointer to the dcache port. Used only for sending. */
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RequestPort *dcachePort;
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/** Particularisation of the LSQSenderState to the LQ. */
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class LQSenderState : public LSQSenderState
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{
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using LSQSenderState::alive;
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public:
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LQSenderState(typename LoadQueue::iterator idx_)
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: LSQSenderState(idx_->request(), true), idx(idx_) { }
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/** The LQ index of the instruction. */
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typename LoadQueue::iterator idx;
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//virtual LSQRequest* request() { return idx->request(); }
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virtual void
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complete()
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{
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//if (alive())
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// idx->request()->senderState(nullptr);
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}
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};
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/** Particularisation of the LSQSenderState to the SQ. */
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class SQSenderState : public LSQSenderState
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{
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using LSQSenderState::alive;
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public:
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SQSenderState(typename StoreQueue::iterator idx_)
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: LSQSenderState(idx_->request(), false), idx(idx_) { }
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/** The SQ index of the instruction. */
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typename StoreQueue::iterator idx;
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//virtual LSQRequest* request() { return idx->request(); }
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virtual void
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complete()
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{
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//if (alive())
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// idx->request()->senderState(nullptr);
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}
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};
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/** Writeback event, specifically for when stores forward data to loads. */
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class WritebackEvent : public Event
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{
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public:
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/** Constructs a writeback event. */
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WritebackEvent(const O3DynInstPtr &_inst, PacketPtr pkt,
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LSQUnit *lsq_ptr);
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/** Processes the writeback event. */
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void process();
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/** Returns the description of this event. */
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const char *description() const;
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private:
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/** Instruction whose results are being written back. */
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O3DynInstPtr inst;
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/** The packet that would have been sent to memory. */
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PacketPtr pkt;
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/** The pointer to the LSQ unit that issued the store. */
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LSQUnit<Impl> *lsqPtr;
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};
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public:
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/**
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* Handles writing back and completing the load or store that has
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* returned from memory.
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*
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* @param pkt Response packet from the memory sub-system
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*/
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bool recvTimingResp(PacketPtr pkt);
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private:
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/** The LSQUnit thread id. */
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ThreadID lsqID;
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public:
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/** The store queue. */
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CircularQueue<SQEntry> storeQueue;
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/** The load queue. */
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LoadQueue loadQueue;
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private:
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/** The number of places to shift addresses in the LSQ before checking
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* for dependency violations
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*/
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unsigned depCheckShift;
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/** Should loads be checked for dependency issues */
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bool checkLoads;
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/** The number of load instructions in the LQ. */
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int loads;
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/** The number of store instructions in the SQ. */
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int stores;
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/** The number of store instructions in the SQ waiting to writeback. */
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int storesToWB;
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// hardware transactional memory
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// nesting depth
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int htmStarts;
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int htmStops;
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// sanity checks and debugging
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uint64_t lastRetiredHtmUid;
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/** The index of the first instruction that may be ready to be
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* written back, and has not yet been written back.
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*/
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typename StoreQueue::iterator storeWBIt;
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/** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
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Addr cacheBlockMask;
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/** Wire to read information from the issue stage time queue. */
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typename TimeBuffer<O3Comm::IssueStruct>::wire fromIssue;
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/** Whether or not the LSQ is stalled. */
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bool stalled;
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/** The store that causes the stall due to partial store to load
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* forwarding.
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*/
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InstSeqNum stallingStoreIsn;
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/** The index of the above store. */
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int stallingLoadIdx;
|
|
|
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/** The packet that needs to be retried. */
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PacketPtr retryPkt;
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|
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/** Whehter or not a store is blocked due to the memory system. */
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|
bool isStoreBlocked;
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|
|
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/** Whether or not a store is in flight. */
|
|
bool storeInFlight;
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|
|
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/** The oldest load that caused a memory ordering violation. */
|
|
O3DynInstPtr memDepViolator;
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|
|
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/** Whether or not there is a packet that couldn't be sent because of
|
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* a lack of cache ports. */
|
|
bool hasPendingRequest;
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|
|
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/** The packet that is pending free cache ports. */
|
|
LSQRequest* pendingRequest;
|
|
|
|
/** Flag for memory model. */
|
|
bool needsTSO;
|
|
|
|
protected:
|
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// Will also need how many read/write ports the Dcache has. Or keep track
|
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// of that in stage that is one level up, and only call executeLoad/Store
|
|
// the appropriate number of times.
|
|
struct LSQUnitStats : public Stats::Group
|
|
{
|
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LSQUnitStats(Stats::Group *parent);
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|
|
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/** Total number of loads forwaded from LSQ stores. */
|
|
Stats::Scalar forwLoads;
|
|
|
|
/** Total number of squashed loads. */
|
|
Stats::Scalar squashedLoads;
|
|
|
|
/** Total number of responses from the memory system that are
|
|
* ignored due to the instruction already being squashed. */
|
|
Stats::Scalar ignoredResponses;
|
|
|
|
/** Tota number of memory ordering violations. */
|
|
Stats::Scalar memOrderViolation;
|
|
|
|
/** Total number of squashed stores. */
|
|
Stats::Scalar squashedStores;
|
|
|
|
/** Number of loads that were rescheduled. */
|
|
Stats::Scalar rescheduledLoads;
|
|
|
|
/** Number of times the LSQ is blocked due to the cache. */
|
|
Stats::Scalar blockedByCache;
|
|
} stats;
|
|
|
|
public:
|
|
/** Executes the load at the given index. */
|
|
Fault read(LSQRequest *req, int load_idx);
|
|
|
|
/** Executes the store at the given index. */
|
|
Fault write(LSQRequest *req, uint8_t *data, int store_idx);
|
|
|
|
/** Returns the index of the head load instruction. */
|
|
int getLoadHead() { return loadQueue.head(); }
|
|
|
|
/** Returns the sequence number of the head load instruction. */
|
|
InstSeqNum
|
|
getLoadHeadSeqNum()
|
|
{
|
|
return loadQueue.front().valid()
|
|
? loadQueue.front().instruction()->seqNum
|
|
: 0;
|
|
}
|
|
|
|
/** Returns the index of the head store instruction. */
|
|
int getStoreHead() { return storeQueue.head(); }
|
|
/** Returns the sequence number of the head store instruction. */
|
|
InstSeqNum
|
|
getStoreHeadSeqNum()
|
|
{
|
|
return storeQueue.front().valid()
|
|
? storeQueue.front().instruction()->seqNum
|
|
: 0;
|
|
}
|
|
|
|
/** Returns whether or not the LSQ unit is stalled. */
|
|
bool isStalled() { return stalled; }
|
|
public:
|
|
typedef typename CircularQueue<LQEntry>::iterator LQIterator;
|
|
typedef typename CircularQueue<SQEntry>::iterator SQIterator;
|
|
typedef CircularQueue<LQEntry> LQueue;
|
|
typedef CircularQueue<SQEntry> SQueue;
|
|
};
|
|
|
|
#endif // __CPU_O3_LSQ_UNIT_HH__
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