a3b1bfdbf0
Being able to recognise pseudo ops from the static instruction pointer is actually quite useful in several circumstances Change-Id: Ib39badf9aabba15ab3ebe7a8e9717583412731e4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
103 lines
5.0 KiB
Python
103 lines
5.0 KiB
Python
# Copyright (c) 2020, 2023 Arm Limited
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2003-2005 The Regents of The University of Michigan
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# Copyright (c) 2013 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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# Set of boolean static instruction properties.
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#
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# Notes:
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# - The IsInteger and IsFloating flags are based on the class of registers
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# accessed by the instruction. Although most instructions will have exactly
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# one of these two flags set, it is possible for an instruction to have
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# neither (e.g., direct unconditional branches, memory barriers) or both
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# (e.g., an FP/int conversion).
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# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect
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# Control will be set, and exactly one of IsCondControl or IsUncondControl
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# will be set.
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class StaticInstFlags(Enum):
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wrapper_name = "StaticInstFlags"
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wrapper_is_struct = True
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enum_name = "Flags"
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vals = [
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"IsNop", # Is a no-op (no effect at all).
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"IsInteger", # References integer regs.
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"IsFloating", # References FP regs.
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"IsVector", # References Vector regs.
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"IsVectorElem", # References Vector reg elems.
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"IsMatrix", # References Matrix regs.
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"IsLoad", # Reads from memory (load or prefetch).
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"IsStore", # Writes to memory.
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"IsAtomic", # Does atomic RMW to memory.
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"IsStoreConditional", # Store conditional instruction.
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"IsInstPrefetch", # Instruction-cache prefetch.
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"IsDataPrefetch", # Data-cache prefetch.
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"IsControl", # Control transfer instruction.
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"IsDirectControl", # PC relative control transfer.
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"IsIndirectControl", # Register indirect control transfer.
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"IsCondControl", # Conditional control transfer.
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"IsUncondControl", # Unconditional control transfer.
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"IsCall", # Subroutine call.
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"IsReturn", # Subroutine return.
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"IsSerializing", # Serializes pipeline: won't execute until all
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# older instructions have committed.
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"IsSerializeBefore",
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"IsSerializeAfter",
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"IsWriteBarrier", # Is a write barrier
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"IsReadBarrier", # Is a read barrier
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"IsNonSpeculative", # Should not be executed speculatively
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"IsQuiesce", # Is a quiesce instruction
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"IsUnverifiable", # Can't be verified by a checker
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"IsPseudo", # Is a gem5 pseudo-op
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"IsSyscall", # Causes a system call to be emulated in syscall
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# emulation mode.
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# Flags for microcode
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"IsMacroop", # Is a macroop containing microops
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"IsMicroop", # Is a microop
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"IsDelayedCommit", # This microop doesn't commit right away
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"IsLastMicroop", # This microop ends a microop sequence
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"IsFirstMicroop", # This microop begins a microop sequence
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"IsSquashAfter", # Squash all uncommitted state after executed
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# hardware transactional memory
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"IsHtmStart", # Starts a HTM transaction
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"IsHtmStop", # Stops (commits) a HTM transaction
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"IsHtmCancel", # Explicitely aborts a HTM transaction
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]
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