e9fcfb3c16
Change-Id: I049f2e97ad00d76341c2aeeaa02279862a8a4d71 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25416 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
322 lines
15 KiB
Python
322 lines
15 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009,2015 Advanced Micro Devices, Inc.
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# Copyright (c) 2013 Mark D. Hill and David A. Wood
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# Copyright (c) 2020 ARM Limited
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from Ruby import create_topology, create_directories
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from Ruby import send_evicts
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from common import FileSystemConfig
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#
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# Declare caches used by the protocol
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#
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class L0Cache(RubyCache): pass
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class L1Cache(RubyCache): pass
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class L2Cache(RubyCache): pass
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def define_options(parser):
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parser.add_option("--num-clusters", type = "int", default = 1,
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help = "number of clusters in a design in which there are shared\
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caches private to clusters")
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parser.add_option("--l0i_size", type="string", default="4096B")
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parser.add_option("--l0d_size", type="string", default="4096B")
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parser.add_option("--l0i_assoc", type="int", default=1)
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parser.add_option("--l0d_assoc", type="int", default=1)
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parser.add_option("--l0_transitions_per_cycle", type="int", default=32)
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parser.add_option("--l1_transitions_per_cycle", type="int", default=32)
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parser.add_option("--l2_transitions_per_cycle", type="int", default=4)
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return
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def create_system(options, full_system, system, dma_ports, bootmem,
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ruby_system):
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if buildEnv['PROTOCOL'] != 'MESI_Three_Level':
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fatal("This script requires the MESI_Three_Level protocol to be\
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built.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes
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# must be listed before the directory nodes and directory nodes before
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# dma nodes, etc.
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#
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l0_cntrl_nodes = []
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l1_cntrl_nodes = []
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l2_cntrl_nodes = []
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dma_cntrl_nodes = []
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assert (options.num_cpus % options.num_clusters == 0)
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num_cpus_per_cluster = options.num_cpus / options.num_clusters
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assert (options.num_l2caches % options.num_clusters == 0)
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num_l2caches_per_cluster = options.num_l2caches / options.num_clusters
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l2_bits = int(math.log(num_l2caches_per_cluster, 2))
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block_size_bits = int(math.log(options.cacheline_size, 2))
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l2_index_start = block_size_bits + l2_bits
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in range(options.num_clusters):
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for j in range(num_cpus_per_cluster):
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#
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# First create the Ruby objects associated with this cpu
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#
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l0i_cache = L0Cache(size = options.l0i_size,
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assoc = options.l0i_assoc,
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is_icache = True,
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start_index_bit = block_size_bits,
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replacement_policy = LRURP())
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l0d_cache = L0Cache(size = options.l0d_size,
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assoc = options.l0d_assoc,
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is_icache = False,
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start_index_bit = block_size_bits,
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replacement_policy = LRURP())
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# the ruby random tester reuses num_cpus to specify the
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# number of cpu ports connected to the tester object, which
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# is stored in system.cpu. because there is only ever one
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# tester object, num_cpus is not necessarily equal to the
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# size of system.cpu; therefore if len(system.cpu) == 1
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# we use system.cpu[0] to set the clk_domain, thereby ensuring
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# we don't index off the end of the cpu list.
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if len(system.cpu) == 1:
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clk_domain = system.cpu[0].clk_domain
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else:
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clk_domain = system.cpu[i].clk_domain
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l0_cntrl = L0Cache_Controller(
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version = i * num_cpus_per_cluster + j,
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Icache = l0i_cache, Dcache = l0d_cache,
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transitions_per_cycle = options.l0_transitions_per_cycle,
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send_evictions = send_evicts(options),
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clk_domain = clk_domain,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j,
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icache = l0i_cache,
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clk_domain = clk_domain,
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dcache = l0d_cache,
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ruby_system = ruby_system)
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l0_cntrl.sequencer = cpu_seq
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l1_cache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc,
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start_index_bit = block_size_bits,
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is_icache = False)
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l1_cntrl = L1Cache_Controller(
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version = i * num_cpus_per_cluster + j,
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cache = l1_cache, l2_select_num_bits = l2_bits,
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cluster_id = i,
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transitions_per_cycle = options.l1_transitions_per_cycle,
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ruby_system = ruby_system)
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exec("ruby_system.l0_cntrl%d = l0_cntrl"
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% ( i * num_cpus_per_cluster + j))
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exec("ruby_system.l1_cntrl%d = l1_cntrl"
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% ( i * num_cpus_per_cluster + j))
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l0_cntrl_nodes.append(l0_cntrl)
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l1_cntrl_nodes.append(l1_cntrl)
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# Connect the L0 and L1 controllers
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l0_cntrl.mandatoryQueue = MessageBuffer()
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l0_cntrl.bufferToL1 = MessageBuffer(ordered = True)
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l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1
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l0_cntrl.bufferFromL1 = MessageBuffer(ordered = True)
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l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1
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# Connect the L1 controllers and the network
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l1_cntrl.requestToL2 = MessageBuffer()
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l1_cntrl.requestToL2.master = ruby_system.network.slave
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l1_cntrl.responseToL2 = MessageBuffer()
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l1_cntrl.responseToL2.master = ruby_system.network.slave
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l1_cntrl.unblockToL2 = MessageBuffer()
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l1_cntrl.unblockToL2.master = ruby_system.network.slave
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l1_cntrl.requestFromL2 = MessageBuffer()
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l1_cntrl.requestFromL2.slave = ruby_system.network.master
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l1_cntrl.responseFromL2 = MessageBuffer()
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l1_cntrl.responseFromL2.slave = ruby_system.network.master
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for j in range(num_l2caches_per_cluster):
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l2_cache = L2Cache(size = options.l2_size,
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assoc = options.l2_assoc,
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start_index_bit = l2_index_start)
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l2_cntrl = L2Cache_Controller(
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version = i * num_l2caches_per_cluster + j,
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L2cache = l2_cache, cluster_id = i,
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transitions_per_cycle =\
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options.l2_transitions_per_cycle,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl"
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% (i * num_l2caches_per_cluster + j))
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l2_cntrl_nodes.append(l2_cntrl)
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# Connect the L2 controllers and the network
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l2_cntrl.DirRequestFromL2Cache = MessageBuffer()
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l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
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l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
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l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
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l2_cntrl.responseFromL2Cache = MessageBuffer()
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l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
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l2_cntrl.unblockToL2Cache = MessageBuffer()
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l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
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l2_cntrl.L1RequestToL2Cache = MessageBuffer()
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l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
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l2_cntrl.responseToL2Cache = MessageBuffer()
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l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
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# Run each of the ruby memory controllers at a ratio of the frequency of
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# the ruby system
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# clk_divider value is a fix to pass regression.
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ruby_system.memctrl_clk_domain = DerivedClockDomain(
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clk_domain = ruby_system.clk_domain, clk_divider = 3)
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mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
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options, bootmem, ruby_system, system)
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dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
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if rom_dir_cntrl_node is not None:
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dir_cntrl_nodes.append(rom_dir_cntrl_node)
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for dir_cntrl in dir_cntrl_nodes:
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# Connect the directory controllers and the network
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dir_cntrl.requestToDir = MessageBuffer()
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dir_cntrl.requestToDir.slave = ruby_system.network.master
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dir_cntrl.responseToDir = MessageBuffer()
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dir_cntrl.responseToDir.slave = ruby_system.network.master
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dir_cntrl.responseFromDir = MessageBuffer()
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dir_cntrl.responseFromDir.master = ruby_system.network.slave
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dir_cntrl.responseFromMemory = MessageBuffer()
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i, ruby_system = ruby_system)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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# Connect the dma controller to the network
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dma_cntrl.mandatoryQueue = MessageBuffer()
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dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
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dma_cntrl.responseFromDir.slave = ruby_system.network.master
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dma_cntrl.requestToDir = MessageBuffer()
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dma_cntrl.requestToDir.master = ruby_system.network.slave
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all_cntrls = l0_cntrl_nodes + \
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l1_cntrl_nodes + \
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l2_cntrl_nodes + \
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dir_cntrl_nodes + \
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dma_cntrl_nodes
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# Create the io controller and the sequencer
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if full_system:
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io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
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ruby_system._io_port = io_seq
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io_controller = DMA_Controller(version = len(dma_ports),
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dma_sequencer = io_seq,
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ruby_system = ruby_system)
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ruby_system.io_controller = io_controller
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# Connect the dma controller to the network
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io_controller.mandatoryQueue = MessageBuffer()
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io_controller.responseFromDir = MessageBuffer(ordered = True)
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io_controller.responseFromDir.slave = ruby_system.network.master
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io_controller.requestToDir = MessageBuffer()
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io_controller.requestToDir.master = ruby_system.network.slave
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all_cntrls = all_cntrls + [io_controller]
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# Register configuration with filesystem
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else:
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for i in xrange(options.num_clusters):
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for j in xrange(num_cpus_per_cluster):
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FileSystemConfig.register_cpu(physical_package_id = 0,
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core_siblings = xrange(options.num_cpus),
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core_id = i*num_cpus_per_cluster+j,
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thread_siblings = [])
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FileSystemConfig.register_cache(level = 0,
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idu_type = 'Instruction',
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size = options.l0i_size,
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line_size =\
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options.cacheline_size,
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assoc = 1,
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cpus = [i*num_cpus_per_cluster+j])
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FileSystemConfig.register_cache(level = 0,
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idu_type = 'Data',
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size = options.l0d_size,
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line_size =\
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options.cacheline_size,
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assoc = 1,
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cpus = [i*num_cpus_per_cluster+j])
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FileSystemConfig.register_cache(level = 1,
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idu_type = 'Unified',
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size = options.l1d_size,
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line_size = options.cacheline_size,
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assoc = options.l1d_assoc,
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cpus = [i*num_cpus_per_cluster+j])
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FileSystemConfig.register_cache(level = 2,
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idu_type = 'Unified',
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size = str(MemorySize(options.l2_size) * \
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num_l2caches_per_cluster)+'B',
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line_size = options.cacheline_size,
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assoc = options.l2_assoc,
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cpus = [n for n in xrange(i*num_cpus_per_cluster, \
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(i+1)*num_cpus_per_cluster)])
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ruby_system.network.number_of_virtual_networks = 3
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topology = create_topology(all_cntrls, options)
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return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
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