e9fcfb3c16
Change-Id: I049f2e97ad00d76341c2aeeaa02279862a8a4d71 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25416 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
256 lines
11 KiB
Python
256 lines
11 KiB
Python
# -*- coding: utf-8 -*-
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# Copyright (c) 2017 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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""" This file creates a set of Ruby caches, the Ruby network, and a simple
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point-to-point topology.
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See Part 3 in the Learning gem5 book:
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http://gem5.org/documentation/learning_gem5/part3/MSIintro
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IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
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also needs to be updated. For now, email Jason <jason@lowepower.com>
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"""
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from __future__ import print_function
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from __future__ import absolute_import
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import math
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from m5.defines import buildEnv
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from m5.util import fatal, panic
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from m5.objects import *
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class MyCacheSystem(RubySystem):
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def __init__(self):
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if buildEnv['PROTOCOL'] != 'MSI':
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fatal("This system assumes MSI from learning gem5!")
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super(MyCacheSystem, self).__init__()
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def setup(self, system, cpus, mem_ctrls):
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"""Set up the Ruby cache subsystem. Note: This can't be done in the
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constructor because many of these items require a pointer to the
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ruby system (self). This causes infinite recursion in initialize()
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if we do this in the __init__.
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"""
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# Ruby's global network.
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self.network = MyNetwork(self)
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# MSI uses 3 virtual networks. One for requests (lowest priority), one
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# for responses (highest priority), and one for "forwards" or
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# cache-to-cache requests. See *.sm files for details.
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self.number_of_virtual_networks = 3
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self.network.number_of_virtual_networks = 3
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# There is a single global list of all of the controllers to make it
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# easier to connect everything to the global network. This can be
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# customized depending on the topology/network requirements.
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# Create one controller for each L1 cache (and the cache mem obj.)
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# Create a single directory controller (Really the memory cntrl)
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self.controllers = \
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[L1Cache(system, self, cpu) for cpu in cpus] + \
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[DirController(self, system.mem_ranges, mem_ctrls)]
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# Create one sequencer per CPU. In many systems this is more
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# complicated since you have to create sequencers for DMA controllers
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# and other controllers, too.
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self.sequencers = [RubySequencer(version = i,
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# I/D cache is combined and grab from ctrl
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icache = self.controllers[i].cacheMemory,
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dcache = self.controllers[i].cacheMemory,
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clk_domain = self.controllers[i].clk_domain,
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) for i in range(len(cpus))]
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# We know that we put the controllers in an order such that the first
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# N of them are the L1 caches which need a sequencer pointer
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for i,c in enumerate(self.controllers[0:len(self.sequencers)]):
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c.sequencer = self.sequencers[i]
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self.num_of_sequencers = len(self.sequencers)
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# Create the network and connect the controllers.
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# NOTE: This is quite different if using Garnet!
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self.network.connectControllers(self.controllers)
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self.network.setup_buffers()
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# Set up a proxy port for the system_port. Used for load binaries and
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# other functional-only things.
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self.sys_port_proxy = RubyPortProxy()
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system.system_port = self.sys_port_proxy.slave
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# Connect the cpu's cache, interrupt, and TLB ports to Ruby
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for i,cpu in enumerate(cpus):
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cpu.icache_port = self.sequencers[i].slave
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cpu.dcache_port = self.sequencers[i].slave
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isa = buildEnv['TARGET_ISA']
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if isa == 'x86':
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cpu.interrupts[0].pio = self.sequencers[i].master
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cpu.interrupts[0].int_master = self.sequencers[i].slave
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cpu.interrupts[0].int_slave = self.sequencers[i].master
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if isa == 'x86' or isa == 'arm':
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cpu.itb.walker.port = self.sequencers[i].slave
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cpu.dtb.walker.port = self.sequencers[i].slave
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class L1Cache(L1Cache_Controller):
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_version = 0
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@classmethod
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def versionCount(cls):
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cls._version += 1 # Use count for this particular type
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return cls._version - 1
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def __init__(self, system, ruby_system, cpu):
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"""CPUs are needed to grab the clock domain and system is needed for
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the cache block size.
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"""
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super(L1Cache, self).__init__()
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self.version = self.versionCount()
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# This is the cache memory object that stores the cache data and tags
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self.cacheMemory = RubyCache(size = '16kB',
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assoc = 8,
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start_index_bit = self.getBlockSizeBits(system))
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self.clk_domain = cpu.clk_domain
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self.send_evictions = self.sendEvicts(cpu)
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self.ruby_system = ruby_system
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self.connectQueues(ruby_system)
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def getBlockSizeBits(self, system):
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bits = int(math.log(system.cache_line_size, 2))
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if 2**bits != system.cache_line_size.value:
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panic("Cache line size not a power of 2!")
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return bits
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def sendEvicts(self, cpu):
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"""True if the CPU model or ISA requires sending evictions from caches
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to the CPU. Two scenarios warrant forwarding evictions to the CPU:
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1. The O3 model must keep the LSQ coherent with the caches
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2. The x86 mwait instruction is built on top of coherence
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3. The local exclusive monitor in ARM systems
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"""
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if type(cpu) is DerivO3CPU or \
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buildEnv['TARGET_ISA'] in ('x86', 'arm'):
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return True
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return False
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def connectQueues(self, ruby_system):
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"""Connect all of the queues for this controller.
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"""
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# mandatoryQueue is a special variable. It is used by the sequencer to
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# send RubyRequests from the CPU (or other processor). It isn't
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# explicitly connected to anything.
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self.mandatoryQueue = MessageBuffer()
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# All message buffers must be created and connected to the general
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# Ruby network. In this case, "slave/master" don't mean the same thing
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# as normal gem5 ports. If a MessageBuffer is a "to" buffer (i.e., out)
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# then you use the "master", otherwise, the slave.
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self.requestToDir = MessageBuffer(ordered = True)
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self.requestToDir.master = ruby_system.network.slave
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self.responseToDirOrSibling = MessageBuffer(ordered = True)
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self.responseToDirOrSibling.master = ruby_system.network.slave
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self.forwardFromDir = MessageBuffer(ordered = True)
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self.forwardFromDir.slave = ruby_system.network.master
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self.responseFromDirOrSibling = MessageBuffer(ordered = True)
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self.responseFromDirOrSibling.slave = ruby_system.network.master
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class DirController(Directory_Controller):
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_version = 0
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@classmethod
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def versionCount(cls):
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cls._version += 1 # Use count for this particular type
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return cls._version - 1
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def __init__(self, ruby_system, ranges, mem_ctrls):
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"""ranges are the memory ranges assigned to this controller.
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"""
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if len(mem_ctrls) > 1:
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panic("This cache system can only be connected to one mem ctrl")
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super(DirController, self).__init__()
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self.version = self.versionCount()
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self.addr_ranges = ranges
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self.ruby_system = ruby_system
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self.directory = RubyDirectoryMemory()
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# Connect this directory to the memory side.
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self.memory = mem_ctrls[0].port
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self.connectQueues(ruby_system)
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def connectQueues(self, ruby_system):
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self.requestFromCache = MessageBuffer(ordered = True)
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self.requestFromCache.slave = ruby_system.network.master
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self.responseFromCache = MessageBuffer(ordered = True)
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self.responseFromCache.slave = ruby_system.network.master
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self.responseToCache = MessageBuffer(ordered = True)
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self.responseToCache.master = ruby_system.network.slave
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self.forwardToCache = MessageBuffer(ordered = True)
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self.forwardToCache.master = ruby_system.network.slave
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# This is another special message buffer. It is used to send replies
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# from memory back to the controller. Any messages received on the
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# memory port (see self.memory above) will be directed to this
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# message buffer.
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self.responseFromMemory = MessageBuffer()
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class MyNetwork(SimpleNetwork):
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"""A simple point-to-point network. This doesn't not use garnet.
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"""
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def __init__(self, ruby_system):
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super(MyNetwork, self).__init__()
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self.netifs = []
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self.ruby_system = ruby_system
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def connectControllers(self, controllers):
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"""Connect all of the controllers to routers and connec the routers
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together in a point-to-point network.
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"""
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# Create one router/switch per controller in the system
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self.routers = [Switch(router_id = i) for i in range(len(controllers))]
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# Make a link from each controller to the router. The link goes
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# externally to the network.
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self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
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int_node=self.routers[i])
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for i, c in enumerate(controllers)]
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# Make an "internal" link (internal to the network) between every pair
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# of routers.
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link_count = 0
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self.int_links = []
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for ri in self.routers:
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for rj in self.routers:
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if ri == rj: continue # Don't connect a router to itself!
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link_count += 1
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self.int_links.append(SimpleIntLink(link_id = link_count,
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src_node = ri,
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dst_node = rj))
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