Steve Reinhardt e9c04dad60 Fix a couple LL/SC bugs that only affected timing mode. ...

src/cpu/simple/timing.cc:
    Fix swap/stq_c command bug.
src/mem/packet.cc:
    Fix incorrect LoadLockedReq command response field.

--HG--
extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5

2007-07-02 09:26:36 -07:00

..

atomic.cc

Make CPU models use new LoadLockedReq/StoreCondReq commands.

2007-06-30 20:35:42 -07:00

atomic.hh

Get rid of Packet result field. Error responses are

2007-06-30 10:16:18 -07:00

AtomicSimpleCPU.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

base.cc

Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.

2007-06-19 18:17:34 +00:00

base.hh

Get rid of Packet result field. Error responses are

2007-06-30 10:16:18 -07:00

SConscript

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

SConsopts

Rework the way SCons recurses into subdirectories, making it

2007-03-10 23:00:54 -08:00

timing.cc

Fix a couple LL/SC bugs that only affected timing mode.

2007-07-02 09:26:36 -07:00

timing.hh

Event descriptions should not end in "event"

2007-06-30 17:45:58 -07:00

TimingSimpleCPU.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00