e9bac9df87
The flow for Full System amdgpu is the use KVM to boot linux and begin loading the driver module. However, the amdgpu module requires reading the VGA ROM located at 0xc0000 in X86. KVM does not support having a small 128KiB hole at this location, therefore we take a checkpoint and switch to a timing CPU to continue loading the drivers before the VGA ROM is read. This creates a checkpoint just before the first MMIOs. This is indicated by three interrupts being sent to the PCI device. After three interrupts in a row are counted a checkpoint exit event occurs. The interrupt counter is reset if a non-interrupt PCI read is seen. Change-Id: I23b320abe81ff6e766cb3f604eca2979339938e5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46161 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
153 lines
7.2 KiB
Python
153 lines
7.2 KiB
Python
# Copyright (c) 2021 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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import m5
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from m5.objects import *
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def createGPU(system, args):
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shader = Shader(n_wf = args.wfs_per_simd,
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timing = True,
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clk_domain = system.clk_domain)
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# VIPER GPU protocol implements release consistency at GPU side. So,
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# we make their writes visible to the global memory and should read
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# from global memory during kernal boundary. The pipeline initiates
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# (or do not initiate) the acquire/release operation depending on
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# these impl_kern_launch_rel and impl_kern_end_rel flags. The flag=true
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# means pipeline initiates a acquire/release operation at kernel launch/end
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# VIPER protocol is write-through based, and thus only impl_kern_launch_acq
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# needs to set.
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shader.impl_kern_launch_acq = True
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shader.impl_kern_end_rel = False
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# Switching off per-lane TLB by default
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per_lane = False
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if args.TLB_config == "perLane":
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per_lane = True
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# List of compute units; one GPU can have multiple compute units
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compute_units = []
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for i in range(args.num_compute_units):
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compute_units.append(
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ComputeUnit(cu_id = i, perLaneTLB = per_lane,
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num_SIMDs = args.simds_per_cu,
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wf_size = args.wf_size,
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spbypass_pipe_length = \
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args.sp_bypass_path_length,
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dpbypass_pipe_length = \
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args.dp_bypass_path_length,
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issue_period = args.issue_period,
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coalescer_to_vrf_bus_width = \
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args.glbmem_rd_bus_width,
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vrf_to_coalescer_bus_width = \
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args.glbmem_wr_bus_width,
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num_global_mem_pipes = \
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args.glb_mem_pipes_per_cu,
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num_shared_mem_pipes = \
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args.shr_mem_pipes_per_cu,
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n_wf = args.wfs_per_simd,
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execPolicy = args.CUExecPolicy,
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localMemBarrier = args.LocalMemBarrier,
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countPages = args.countPages,
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localDataStore = \
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LdsState(banks = args.numLdsBanks,
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bankConflictPenalty = \
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args.ldsBankConflictPenalty,
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size = args.lds_size)))
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wavefronts = []
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vrfs = []
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vrf_pool_mgrs = []
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srfs = []
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srf_pool_mgrs = []
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for j in range(args.simds_per_cu):
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for k in range(shader.n_wf):
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wavefronts.append(Wavefront(simdId = j, wf_slot_id = k,
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wf_size = args.wf_size))
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if args.reg_alloc_policy == "simple":
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vrf_pool_mgrs.append(SimplePoolManager(pool_size = \
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args.vreg_file_size,
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min_alloc = \
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args.vreg_min_alloc))
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srf_pool_mgrs.append(SimplePoolManager(pool_size = \
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args.sreg_file_size,
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min_alloc = \
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args.vreg_min_alloc))
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elif args.reg_alloc_policy == "dynamic":
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vrf_pool_mgrs.append(DynPoolManager(pool_size = \
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args.vreg_file_size,
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min_alloc = \
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args.vreg_min_alloc))
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srf_pool_mgrs.append(DynPoolManager(pool_size = \
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args.sreg_file_size,
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min_alloc = \
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args.vreg_min_alloc))
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vrfs.append(VectorRegisterFile(simd_id=j, wf_size=args.wf_size,
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num_regs=args.vreg_file_size))
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srfs.append(ScalarRegisterFile(simd_id=j, wf_size=args.wf_size,
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num_regs=args.sreg_file_size))
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compute_units[-1].wavefronts = wavefronts
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compute_units[-1].vector_register_file = vrfs
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compute_units[-1].scalar_register_file = srfs
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compute_units[-1].register_manager = \
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RegisterManager(policy=args.registerManagerPolicy,
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vrf_pool_managers=vrf_pool_mgrs,
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srf_pool_managers=srf_pool_mgrs)
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if args.TLB_prefetch:
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compute_units[-1].prefetch_depth = args.TLB_prefetch
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compute_units[-1].prefetch_prev_type = args.pf_type
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# Attach the LDS and the CU to the bus (actually a Bridge)
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compute_units[-1].ldsPort = compute_units[-1].ldsBus.cpu_side_port
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compute_units[-1].ldsBus.mem_side_port = \
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compute_units[-1].localDataStore.cuPort
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# Attach compute units to GPU
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shader.CUs = compute_units
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shader.cpu_pointer = system.cpu[0]
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shader.eventq_index = 0
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shader.set_parent(system, "Shader")
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return shader
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def connectGPU(system, args):
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system.pc.south_bridge.gpu = AMDGPUDevice(pci_func=0, pci_dev=8, pci_bus=0)
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system.pc.south_bridge.gpu.trace_file = args.gpu_mmio_trace
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system.pc.south_bridge.gpu.rom_binary = args.gpu_rom
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system.pc.south_bridge.gpu.checkpoint_before_mmios = \
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args.checkpoint_before_mmios
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