568fa11084
src/arch/alpha/isa_traits.hh:
This got changed to the wrong version by accident.
src/cpu/base.cc:
Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
Switch out updates from the version of m5 I have. Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
Use proper method to get flags. Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
Support profiling.
src/cpu/ozone/cpu.hh:
Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
Get flags correctly.
src/cpu/ozone/thread_state.hh:
Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext.
--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
58 lines
2.0 KiB
Python
58 lines
2.0 KiB
Python
from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from m5 import build_env
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from AlphaTLB import AlphaDTB, AlphaITB
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from Bus import Bus
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class BaseCPU(SimObject):
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type = 'BaseCPU'
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abstract = True
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mem = Param.MemObject("memory")
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system = Param.System(Parent.any, "system object")
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if build_env['FULL_SYSTEM']:
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dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
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cpu_id = Param.Int(-1, "CPU identifier")
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else:
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workload = VectorParam.Process("processes to run")
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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progress_interval = Param.Tick(0, "interval to print out the progress message")
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defer_registration = Param.Bool(False,
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"defer registration with system (for sampling)")
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clock = Param.Clock(Parent.clock, "clock speed")
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_mem_ports = []
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def connectMemPorts(self, bus):
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for p in self._mem_ports:
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exec('self.%s = bus.port' % p)
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def addPrivateSplitL1Caches(self, ic, dc):
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assert(len(self._mem_ports) == 2)
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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# self.mem = dc
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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self.toL2Bus = Bus()
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self.connectMemPorts(self.toL2Bus)
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self.l2cache = l2c
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self.l2cache.cpu_side = self.toL2Bus.port
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self._mem_ports = ['l2cache.mem_side']
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